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Searched refs:link_width_cntl (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770.c1975 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
1998 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
1999 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable()
2000 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
2001 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable()
2002 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable()
2003 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2004 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable()
2006 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
2008 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable()
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Dr300.c501 uint32_t link_width_cntl, mask; in rv370_set_pcie_lanes() local
536 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
538 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == in rv370_set_pcie_lanes()
542 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | in rv370_set_pcie_lanes()
546 link_width_cntl |= mask; in rv370_set_pcie_lanes()
547 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv370_set_pcie_lanes()
548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | in rv370_set_pcie_lanes()
552 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
553 while (link_width_cntl == 0xffffffff) in rv370_set_pcie_lanes()
554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
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Dr600.c4354 u32 link_width_cntl, mask; in r600_set_pcie_lanes() local
4396 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_set_pcie_lanes()
4397 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; in r600_set_pcie_lanes()
4398 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; in r600_set_pcie_lanes()
4399 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | in r600_set_pcie_lanes()
4402 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in r600_set_pcie_lanes()
4407 u32 link_width_cntl; in r600_get_pcie_lanes() local
4421 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in r600_get_pcie_lanes()
4423 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF… in r600_get_pcie_lanes()
4444 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
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Devergreen.c5867 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local
5897 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5898 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5899 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
5918 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable()
5921 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5923 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable()
5924 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()