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Searched refs:mmSDMA0_GFX_IB_CNTL (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c70 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
89 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
108 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
128 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
495 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
497 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop()
645 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
651 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_resume()
1259 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); in sdma_v3_0_print_status()
Dsdma_v2_4.c384 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
386 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop()
497 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
503 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_resume()
1099 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); in sdma_v2_4_print_status()
Dcik_sdma.c344 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
460 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in cik_sdma_gfx_resume()
1088 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); in cik_sdma_print_status()
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h197 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
Doss_3_0_1_d.h224 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
Doss_3_0_d.h349 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
Doss_2_0_d.h256 #define mmSDMA0_GFX_IB_CNTL 0x348a macro