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Searched refs:mmSDMA0_TILING_CONFIG (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h163 #define mmSDMA0_TILING_CONFIG 0x3406 macro
Doss_3_0_1_d.h160 #define mmSDMA0_TILING_CONFIG 0x3406 macro
Doss_3_0_d.h297 #define mmSDMA0_TILING_CONFIG 0x3406 macro
Doss_2_0_d.h225 #define mmSDMA0_TILING_CONFIG 0x3406 macro
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v7_0.c2206 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
2207 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in gfx_v7_0_gpu_init()
4988 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); in gfx_v7_0_print_status()
4990 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); in gfx_v7_0_print_status()
Dgfx_v8_0.c2902 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, in gfx_v8_0_gpu_init()
2904 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, in gfx_v8_0_gpu_init()
4167 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET)); in gfx_v8_0_print_status()
4169 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET)); in gfx_v8_0_print_status()