Home
last modified time | relevance | path

Searched refs:mmSRBM_STATUS (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dcik_ih.c345 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
361 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; in cik_ih_wait_for_idle()
375 RREG32(mmSRBM_STATUS)); in cik_ih_print_status()
403 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
Dcz_ih.c323 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
339 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
353 RREG32(mmSRBM_STATUS)); in cz_ih_print_status()
380 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
Diceland_ih.c323 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
339 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
353 RREG32(mmSRBM_STATUS)); in iceland_ih_print_status()
380 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
Dtonga_ih.c346 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_is_idle()
362 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_wait_for_idle()
376 RREG32(mmSRBM_STATUS)); in tonga_ih_print_status()
403 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_soft_reset()
Dgmc_v8_0.c137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | in gmc_v8_0_mc_wait_for_idle()
1048 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_is_idle()
1065 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v8_0_wait_for_idle()
1086 RREG32(mmSRBM_STATUS)); in gmc_v8_0_print_status()
1189 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_soft_reset()
Dgmc_v7_0.c92 tmp = RREG32(mmSRBM_STATUS) & 0x1F00; in gmc_v7_0_mc_wait_for_idle()
1088 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_is_idle()
1105 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v7_0_wait_for_idle()
1125 RREG32(mmSRBM_STATUS)); in gmc_v7_0_print_status()
1231 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v7_0_soft_reset()
Duvd_v5_0.c620 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v5_0_is_idle()
629 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v5_0_wait_for_idle()
Duvd_v6_0.c612 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v6_0_is_idle()
621 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v6_0_wait_for_idle()
Duvd_v4_2.c677 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); in uvd_v4_2_is_idle()
686 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) in uvd_v4_2_wait_for_idle()
Dvi.c399 {mmSRBM_STATUS, false},
555 RREG32(mmSRBM_STATUS)); in vi_print_gpu_status_regs()
628 tmp = RREG32(mmSRBM_STATUS); in vi_gpu_check_soft_reset()
Dcik.c1044 RREG32(mmSRBM_STATUS)); in cik_print_gpu_status_regs()
1120 tmp = RREG32(mmSRBM_STATUS); in amdgpu_cik_gpu_check_soft_reset()
Dgfx_v7_0.c5216 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
Dgfx_v8_0.c4330 tmp = RREG32(mmSRBM_STATUS); in gfx_v8_0_soft_reset()
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h81 #define mmSRBM_STATUS 0x394 macro
Doss_3_0_1_d.h79 #define mmSRBM_STATUS 0x394 macro
Doss_3_0_d.h91 #define mmSRBM_STATUS 0x394 macro
Doss_2_0_d.h74 #define mmSRBM_STATUS 0x394 macro