Searched refs:mmSRBM_STATUS2 (Results 1 – 17 of 17) sorted by relevance
455 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); in vce_v2_0_is_idle()464 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)) in vce_v2_0_wait_for_idle()
1055 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v2_4_is_idle()1071 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | in sdma_v2_4_wait_for_idle()1088 RREG32(mmSRBM_STATUS2)); in sdma_v2_4_print_status()1132 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v2_4_soft_reset()
452 return !(RREG32(mmSRBM_STATUS2) & mask); in vce_v3_0_is_idle()473 if (!(RREG32(mmSRBM_STATUS2) & mask)) in vce_v3_0_wait_for_idle()
1215 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v3_0_is_idle()1231 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | in sdma_v3_0_wait_for_idle()1248 RREG32(mmSRBM_STATUS2)); in sdma_v3_0_print_status()1294 u32 tmp = RREG32(mmSRBM_STATUS2); in sdma_v3_0_soft_reset()
400 {mmSRBM_STATUS2, false},557 RREG32(mmSRBM_STATUS2)); in vi_print_gpu_status_regs()620 tmp = RREG32(mmSRBM_STATUS2); in vi_gpu_check_soft_reset()
1042 u32 tmp = RREG32(mmSRBM_STATUS2); in cik_sdma_is_idle()1058 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | in cik_sdma_wait_for_idle()1075 RREG32(mmSRBM_STATUS2)); in cik_sdma_print_status()
377 RREG32(mmSRBM_STATUS2)); in cik_ih_print_status()
355 RREG32(mmSRBM_STATUS2)); in cz_ih_print_status()
355 RREG32(mmSRBM_STATUS2)); in iceland_ih_print_status()
378 RREG32(mmSRBM_STATUS2)); in tonga_ih_print_status()
1046 RREG32(mmSRBM_STATUS2)); in cik_print_gpu_status_regs()1112 tmp = RREG32(mmSRBM_STATUS2); in amdgpu_cik_gpu_check_soft_reset()
1088 RREG32(mmSRBM_STATUS2)); in gmc_v8_0_print_status()
1127 RREG32(mmSRBM_STATUS2)); in gmc_v7_0_print_status()
80 #define mmSRBM_STATUS2 0x393 macro
78 #define mmSRBM_STATUS2 0x393 macro
90 #define mmSRBM_STATUS2 0x393 macro
73 #define mmSRBM_STATUS2 0x393 macro