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Searched refs:mmUVD_MPC_SET_MUXA0 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_d.h53 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
Duvd_6_0_d.h60 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
Duvd_5_0_d.h59 #define mmUVD_MPC_SET_MUXA0 0x3d79 macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c342 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v5_0_start()
697 RREG32(mmUVD_MPC_SET_MUXA0)); in uvd_v5_0_print_status()
Duvd_v6_0.c340 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v6_0_start()
689 RREG32(mmUVD_MPC_SET_MUXA0)); in uvd_v6_0_print_status()
Duvd_v4_2.c307 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); in uvd_v4_2_start()
754 RREG32(mmUVD_MPC_SET_MUXA0)); in uvd_v4_2_print_status()