Home
last modified time | relevance | path

Searched refs:mmUVD_VCPU_CACHE_OFFSET0 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_d.h59 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_6_0_d.h66 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
Duvd_5_0_d.h65 #define mmUVD_VCPU_CACHE_OFFSET0 0x3d82 macro
/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c270 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v5_0_mc_resume()
709 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); in uvd_v5_0_print_status()
Duvd_v6_0.c268 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); in uvd_v6_0_mc_resume()
701 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); in uvd_v6_0_print_status()
Duvd_v4_2.c585 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); in uvd_v4_2_mc_resume()
766 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); in uvd_v4_2_print_status()