| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | outpdp.c | 36 struct nvkm_output_dp *outp = nvkm_output_dp(base); in nvkm_output_dp_train() local
43 ret = nvkm_rdaux(outp->aux, DPCD_LC00_LINK_BW_SET, link, 2); in nvkm_output_dp_train()
45 OUTP_DBG(&outp->base, in nvkm_output_dp_train()
54 OUTP_DBG(&outp->base, "link not trained at sufficient rate"); in nvkm_output_dp_train()
59 ret = nvkm_rdaux(outp->aux, DPCD_LS02, stat, 3); in nvkm_output_dp_train()
61 OUTP_DBG(&outp->base, in nvkm_output_dp_train()
72 OUTP_DBG(&outp->base, in nvkm_output_dp_train()
79 OUTP_DBG(&outp->base, "no inter-lane alignment"); in nvkm_output_dp_train()
83 if (retrain || !atomic_read(&outp->lt.done)) { in nvkm_output_dp_train()
85 if (outp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) { in nvkm_output_dp_train()
[all …]
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| D | dport.c | 38 struct nvkm_output_dp *outp; member
51 struct nvkm_output_dp *outp = dp->outp; in dp_set_link_config() local
52 struct nvkm_disp *disp = outp->base.disp; in dp_set_link_config()
59 .outp = &outp->base.info, in dp_set_link_config()
67 OUTP_DBG(&outp->base, "%d lanes at %d KB/s", dp->link_nr, dp->link_bw); in dp_set_link_config()
70 if ((lnkcmp = dp->outp->info.lnkcmp)) { in dp_set_link_config()
71 if (outp->version < 0x30) { in dp_set_link_config()
84 ret = outp->func->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, in dp_set_link_config()
85 outp->dpcd[DPCD_RC02] & in dp_set_link_config()
89 OUTP_ERR(&outp->base, "lnk_ctl failed with %d", ret); in dp_set_link_config()
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| D | outp.c | 31 nvkm_output_fini(struct nvkm_output *outp) in nvkm_output_fini() argument
33 if (outp->func->fini) in nvkm_output_fini()
34 outp->func->fini(outp); in nvkm_output_fini()
38 nvkm_output_init(struct nvkm_output *outp) in nvkm_output_init() argument
40 if (outp->func->init) in nvkm_output_init()
41 outp->func->init(outp); in nvkm_output_init()
47 struct nvkm_output *outp = *poutp; in nvkm_output_del() local
48 if (outp && !WARN_ON(!outp->func)) { in nvkm_output_del()
49 if (outp->func->dtor) in nvkm_output_del()
50 *poutp = outp->func->dtor(outp); in nvkm_output_del()
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| D | base.c | 98 struct nvkm_output *outp; in nvkm_disp_hpd_ctor() local
103 list_for_each_entry(outp, &disp->outp, head) { in nvkm_disp_hpd_ctor()
104 if (ret = -ENXIO, outp->conn->index == req->v0.conn) { in nvkm_disp_hpd_ctor()
105 if (ret = -ENODEV, outp->conn->hpd.event) { in nvkm_disp_hpd_ctor()
213 struct nvkm_output *outp; in nvkm_disp_fini() local
215 list_for_each_entry(outp, &disp->outp, head) { in nvkm_disp_fini()
216 nvkm_output_fini(outp); in nvkm_disp_fini()
231 struct nvkm_output *outp; in nvkm_disp_init() local
237 list_for_each_entry(outp, &disp->outp, head) { in nvkm_disp_init()
238 nvkm_output_init(outp); in nvkm_disp_init()
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| D | nv50.c | 47 return disp->func->outp.internal.crt(base, index, dcb, poutp); in nv50_disp_outp_internal_crt_()
56 return disp->func->outp.internal.tmds(base, index, dcb, poutp); in nv50_disp_outp_internal_tmds_()
65 return disp->func->outp.internal.lvds(base, index, dcb, poutp); in nv50_disp_outp_internal_lvds_()
73 if (disp->func->outp.internal.dp) in nv50_disp_outp_internal_dp_()
74 return disp->func->outp.internal.dp(base, index, dcb, poutp); in nv50_disp_outp_internal_dp_()
84 if (disp->func->outp.external.tmds) in nv50_disp_outp_external_tmds_()
85 return disp->func->outp.external.tmds(base, index, dcb, poutp); in nv50_disp_outp_external_tmds_()
94 if (disp->func->outp.external.dp) in nv50_disp_outp_external_dp_()
95 return disp->func->outp.external.dp(base, index, dcb, poutp); in nv50_disp_outp_external_dp_()
133 .outp.internal.crt = nv50_disp_outp_internal_crt_,
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| D | sorgm204.c | 30 gm204_sor_soff(struct nvkm_output_dp *outp) in gm204_sor_soff() argument
32 return (ffs(outp->base.info.or) - 1) * 0x800; in gm204_sor_soff()
36 gm204_sor_loff(struct nvkm_output_dp *outp) in gm204_sor_loff() argument
38 return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; in gm204_sor_loff()
42 gm204_sor_magic(struct nvkm_output *outp) in gm204_sor_magic() argument
44 struct nvkm_device *device = outp->disp->engine.subdev.device; in gm204_sor_magic()
45 const u32 soff = outp->or * 0x100; in gm204_sor_magic()
46 const u32 data = outp->or + 1; in gm204_sor_magic()
47 if (outp->info.sorconf.link & 1) in gm204_sor_magic()
49 if (outp->info.sorconf.link & 2) in gm204_sor_magic()
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| D | sorg94.c | 30 g94_sor_soff(struct nvkm_output_dp *outp) in g94_sor_soff() argument
32 return (ffs(outp->base.info.or) - 1) * 0x800; in g94_sor_soff()
36 g94_sor_loff(struct nvkm_output_dp *outp) in g94_sor_loff() argument
38 return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; in g94_sor_loff()
73 g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) in g94_sor_dp_pattern() argument
75 struct nvkm_device *device = outp->base.disp->engine.subdev.device; in g94_sor_dp_pattern()
76 const u32 loff = g94_sor_loff(outp); in g94_sor_dp_pattern()
82 g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) in g94_sor_dp_lnk_pwr() argument
84 struct nvkm_device *device = outp->base.disp->engine.subdev.device; in g94_sor_dp_lnk_pwr()
85 const u32 soff = g94_sor_soff(outp); in g94_sor_dp_lnk_pwr()
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| D | gf119.c | 54 struct nvkm_output *outp; in exec_lookup() local
79 list_for_each_entry(outp, &disp->base.outp, head) { in exec_lookup()
80 if ((outp->info.hasht & 0xff) == type && in exec_lookup()
81 (outp->info.hashm & mask) == mask) { in exec_lookup()
82 *data = nvbios_outp_match(bios, outp->info.hasht, in exec_lookup()
83 outp->info.hashm, in exec_lookup()
87 return outp; in exec_lookup()
100 struct nvkm_output *outp; in exec_script() local
115 outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); in exec_script()
116 if (outp) { in exec_script()
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| D | sorgf119.c | 28 gf119_sor_soff(struct nvkm_output_dp *outp) in gf119_sor_soff() argument
30 return (ffs(outp->base.info.or) - 1) * 0x800; in gf119_sor_soff()
34 gf119_sor_loff(struct nvkm_output_dp *outp) in gf119_sor_loff() argument
36 return gf119_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; in gf119_sor_loff()
40 gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) in gf119_sor_dp_pattern() argument
42 struct nvkm_device *device = outp->base.disp->engine.subdev.device; in gf119_sor_dp_pattern()
43 const u32 soff = gf119_sor_soff(outp); in gf119_sor_dp_pattern()
49 gf119_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) in gf119_sor_dp_lnk_ctl() argument
51 struct nvkm_device *device = outp->base.disp->engine.subdev.device; in gf119_sor_dp_lnk_ctl()
52 const u32 soff = gf119_sor_soff(outp); in gf119_sor_dp_lnk_ctl()
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| D | piornv50.c | 38 const u32 soff = outp->or * 0x800; in nv50_pior_power()
65 disp->pior.type[outp->or] = type; in nv50_pior_power()
88 nv50_pior_output_dp_pattern(struct nvkm_output_dp *outp, int pattern) in nv50_pior_output_dp_pattern() argument
94 nv50_pior_output_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) in nv50_pior_output_dp_lnk_pwr() argument
100 nv50_pior_output_dp_lnk_ctl(struct nvkm_output_dp *outp, in nv50_pior_output_dp_lnk_ctl() argument
103 int ret = nvkm_i2c_aux_lnk_ctl(outp->aux, nr, bw, ef); in nv50_pior_output_dp_lnk_ctl()
123 struct nvkm_output_dp *outp; in nv50_pior_dp_new() local
125 if (!(outp = kzalloc(sizeof(*outp), GFP_KERNEL))) in nv50_pior_dp_new()
127 *poutp = &outp->base; in nv50_pior_dp_new()
130 index, dcbE, aux, outp); in nv50_pior_dp_new()
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| D | g94.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = g94_sor_dp_new,
40 .outp.external.tmds = nv50_pior_output_new,
41 .outp.external.dp = nv50_pior_dp_new,
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| D | gt215.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = g94_sor_dp_new,
40 .outp.external.tmds = nv50_pior_output_new,
41 .outp.external.dp = nv50_pior_dp_new,
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| D | g84.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.external.tmds = nv50_pior_output_new,
40 .outp.external.dp = nv50_pior_dp_new,
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| D | gt200.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.external.tmds = nv50_pior_output_new,
40 .outp.external.dp = nv50_pior_dp_new,
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| D | rootnv50.c | 78 struct nvkm_output *outp = NULL; in nv50_disp_root_mthd_() local
109 list_for_each_entry(temp, &disp->base.outp, head) { in nv50_disp_root_mthd_()
112 outp = temp; in nv50_disp_root_mthd_()
116 if (outp == NULL) in nv50_disp_root_mthd_()
127 switch (mthd * !!outp) { in nv50_disp_root_mthd_()
129 return func->dac.power(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
131 return func->dac.sense(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
133 return func->sor.power(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
137 return func->sor.hda_eld(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
141 return func->sor.hdmi(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
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| D | gk104.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = gf119_sor_dp_new,
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| D | gm107.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = gf119_sor_dp_new,
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| D | gk110.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = gf119_sor_dp_new,
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| D | gm204.c | 36 .outp.internal.crt = nv50_dac_output_new,
37 .outp.internal.tmds = nv50_sor_output_new,
38 .outp.internal.lvds = nv50_sor_output_new,
39 .outp.internal.dp = gm204_sor_dp_new,
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | dcb.c | 109 dcb_outp_hasht(struct dcb_output *outp) in dcb_outp_hasht() argument
111 return (outp->extdev << 8) | (outp->location << 4) | outp->type; in dcb_outp_hasht()
115 dcb_outp_hashm(struct dcb_output *outp) in dcb_outp_hashm() argument
117 return (outp->heads << 8) | (outp->link << 6) | outp->or; in dcb_outp_hashm()
122 struct dcb_output *outp) in dcb_outp_parse() argument
125 memset(outp, 0x00, sizeof(*outp)); in dcb_outp_parse()
129 outp->or = (conn & 0x0f000000) >> 24; in dcb_outp_parse()
130 outp->location = (conn & 0x00300000) >> 20; in dcb_outp_parse()
131 outp->bus = (conn & 0x000f0000) >> 16; in dcb_outp_parse()
132 outp->connector = (conn & 0x0000f000) >> 12; in dcb_outp_parse()
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| D | dp.c | 63 u16 outp = nvbios_rd16(bios, data + *hdr + idx * *len); in nvbios_dpout_entry() local
64 switch (*ver * !!outp) { in nvbios_dpout_entry()
69 *cnt = nvbios_rd08(bios, outp + 0x04); in nvbios_dpout_entry()
80 return outp; in nvbios_dpout_entry()
144 nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx, in nvbios_dpcfg_entry() argument
148 outp = nvbios_dp_table(bios, ver, hdr, cnt, len); in nvbios_dpcfg_entry()
150 *len = nvbios_rd08(bios, outp + 0x06); in nvbios_dpcfg_entry()
151 *cnt = nvbios_rd08(bios, outp + 0x07) * in nvbios_dpcfg_entry()
152 nvbios_rd08(bios, outp + 0x05); in nvbios_dpcfg_entry()
156 return outp + *hdr + (idx * *len); in nvbios_dpcfg_entry()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/mxm/ |
| D | nv50.c | 32 u32 *outp; member
59 if ((ctx->outp[0] & 0x0000000f) != ctx->desc.outp_type) in mxm_match_dcb()
69 if ((ctx->outp[0] & 0x0f000000) != (link & 0x0f) << 24) in mxm_match_dcb()
74 if ((link & ((ctx->outp[1] & 0x00000030) >> 4)) != link) in mxm_match_dcb()
98 struct context ctx = { .outp = (u32 *)(bios->data + pdcb) }; in mxm_dcb_sanitise_entry()
107 idx, ctx.outp[0], ctx.outp[1]); in mxm_dcb_sanitise_entry()
108 ctx.outp[0] |= 0x0000000f; in mxm_dcb_sanitise_entry()
117 if ((ctx.outp[0] & 0x0000000f) != DCB_OUTPUT_DP) in mxm_dcb_sanitise_entry()
123 ctx.outp[0] &= ~0x000000f0; in mxm_dcb_sanitise_entry()
124 ctx.outp[0] |= i2cidx; in mxm_dcb_sanitise_entry()
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| /drivers/net/fddi/skfp/ |
| D | drvfbi.c | 103 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ; in card_start()
108 outp(ADDR(B0_CTRL),CTRL_RST_SET) ; /* reset for all chips */ in card_start()
111 outp(ADDR(B0_CTRL), CTRL_RST_CLR) ; in card_start()
116 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_ON) ; /* enable for writes */ in card_start()
119 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_OFF) ; /* disable writes */ in card_start()
126 outp(ADDR(B0_CTRL), CTRL_MRST_CLR|CTRL_HPI_CLR) ; in card_start()
150 outp(ADDR(B0_CTRL),CTRL_RST_CLR) ; /* clear the reset chips */ in card_start()
151 outp(ADDR(B0_LED),LED_GA_OFF|LED_MY_ON|LED_GB_OFF) ; /* ye LED on */ in card_start()
173 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ; in card_stop()
178 outp(ADDR(B0_CTRL),CTRL_RST_SET) ; /* reset for all chips */ in card_stop()
[all …]
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| /drivers/hwtracing/intel_th/ |
| D | sth.c | 78 u64 __iomem *outp = &out->Dn; in sth_stm_packet() local
106 outp = (u64 __iomem *)&out->FLAG_TS; in sth_stm_packet()
108 outp = (u64 __iomem *)&out->FLAG; in sth_stm_packet()
111 sth_iowrite(outp, payload, size); in sth_stm_packet()
116 outp = &out->USER_TS; in sth_stm_packet()
118 outp = &out->USER; in sth_stm_packet()
119 sth_iowrite(outp, payload, size); in sth_stm_packet()
123 outp = &out->Dn; in sth_stm_packet()
126 outp += 2; in sth_stm_packet()
128 outp++; in sth_stm_packet()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv50.c | 130 struct dcb_output outp; in nv50_devinit_init() local
138 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { in nv50_devinit_init()
139 if (nvbios_outp_match(bios, outp.hasht, outp.hashm, in nv50_devinit_init()
145 .outp = &outp, in nv50_devinit_init()
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