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Searched refs:pfit_control (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_panel.c227 u32 *pfit_control) in i965_scale_aspect() argument
237 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
240 *pfit_control |= PFIT_ENABLE | in i965_scale_aspect()
243 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; in i965_scale_aspect()
247 u32 *pfit_control, u32 *pfit_pgm_ratios, in i9xx_scale_aspect() argument
274 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
290 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
296 *pfit_control |= (PFIT_ENABLE | in i9xx_scale_aspect()
308 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; in intel_gmch_panel_fitting() local
329 i965_scale_aspect(pipe_config, &pfit_control); in intel_gmch_panel_fitting()
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Dintel_overlay.c899 u32 pfit_control = I915_READ(PFIT_CONTROL); in update_pfit_vscale_ratio() local
909 if (pfit_control & VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
1066 u32 pfit_control; in intel_panel_fitter_pipe() local
1072 pfit_control = I915_READ(PFIT_CONTROL); in intel_panel_fitter_pipe()
1075 if ((pfit_control & PFIT_ENABLE) == 0) in intel_panel_fitter_pipe()
1080 return (pfit_control >> 29) & 0x3; in intel_panel_fitter_pipe()
/drivers/gpu/drm/gma500/
Dcdv_intel_lvds.c360 u32 pfit_control; in cdv_intel_lvds_mode_set() local
375 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in cdv_intel_lvds_mode_set()
379 pfit_control = 0; in cdv_intel_lvds_mode_set()
381 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_lvds_mode_set()
384 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in cdv_intel_lvds_mode_set()
386 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_lvds_mode_set()
Dpsb_intel_lvds.c475 u32 pfit_control; in psb_intel_lvds_mode_set() local
490 pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | in psb_intel_lvds_mode_set()
494 pfit_control = 0; in psb_intel_lvds_mode_set()
497 pfit_control |= PANEL_8TO6_DITHER_ENABLE; in psb_intel_lvds_mode_set()
499 REG_WRITE(PFIT_CONTROL, pfit_control); in psb_intel_lvds_mode_set()
Doaktrail_crtc.c356 u32 pfit_control; in oaktrail_panel_fitter_pipe() local
358 pfit_control = REG_READ(PFIT_CONTROL); in oaktrail_panel_fitter_pipe()
361 if ((pfit_control & PFIT_ENABLE) == 0) in oaktrail_panel_fitter_pipe()
363 return (pfit_control >> 29) & 3; in oaktrail_panel_fitter_pipe()
Dpsb_intel_display.c91 u32 pfit_control; in psb_intel_panel_fitter_pipe() local
93 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
96 if ((pfit_control & PFIT_ENABLE) == 0) in psb_intel_panel_fitter_pipe()
Dmdfld_intel_display.c113 u32 pfit_control; in psb_intel_panel_fitter_pipe() local
115 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
118 if ((pfit_control & PFIT_ENABLE) == 0) in psb_intel_panel_fitter_pipe()
122 return (pfit_control >> 29) & 0x3; in psb_intel_panel_fitter_pipe()
Dcdv_intel_display.c570 u32 pfit_control; in cdv_intel_panel_fitter_pipe() local
572 pfit_control = REG_READ(PFIT_CONTROL); in cdv_intel_panel_fitter_pipe()
575 if ((pfit_control & PFIT_ENABLE) == 0) in cdv_intel_panel_fitter_pipe()
577 return (pfit_control >> 29) & 0x3; in cdv_intel_panel_fitter_pipe()
Dcdv_intel_dp.c1091 uint32_t pfit_control; in cdv_intel_dp_mode_set() local
1096 pfit_control = PFIT_ENABLE; in cdv_intel_dp_mode_set()
1098 pfit_control = 0; in cdv_intel_dp_mode_set()
1100 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; in cdv_intel_dp_mode_set()
1102 REG_WRITE(PFIT_CONTROL, pfit_control); in cdv_intel_dp_mode_set()