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Searched refs:phases (Results 1 – 11 of 11) sorted by relevance

/drivers/nfc/pn544/
Dpn544.c347 u8 phases = 0; in pn544_hci_start_poll() local
378 phases |= 1; /* Type A */ in pn544_hci_start_poll()
380 phases |= (1 << 2); /* Type F 212 */ in pn544_hci_start_poll()
381 phases |= (1 << 3); /* Type F 424 */ in pn544_hci_start_poll()
384 phases |= (1 << 5); /* NFC active */ in pn544_hci_start_poll()
387 PN544_PL_RDPHASES, &phases, 1); in pn544_hci_start_poll()
/drivers/gpu/drm/i915/
Di915_gem_shrinker.c81 } phases[] = { in i915_gem_shrink() local
110 for (phase = phases; phase->list; phase++) { in i915_gem_shrink()
/drivers/vfio/pci/
Dvfio_pci_config.c1147 int ret, evcc, phases, vc_arb; in vfio_vc_cap_len() local
1160 phases = 128; in vfio_vc_cap_len()
1162 phases = 64; in vfio_vc_cap_len()
1164 phases = 32; in vfio_vc_cap_len()
1166 phases = 0; in vfio_vc_cap_len()
1168 vc_arb = phases * 4; in vfio_vc_cap_len()
/drivers/scsi/arm/
Dfas216.c250 static const char *phases[] = { in fas216_bus_phase() local
257 return phases[stat & STAT_BUSMASK]; in fas216_bus_phase()
262 static const char *phases[] = { in fas216_drv_phase() local
276 if (info->scsi.phase < ARRAY_SIZE(phases) && in fas216_drv_phase()
277 phases[info->scsi.phase]) in fas216_drv_phase()
278 return phases[info->scsi.phase]; in fas216_drv_phase()
/drivers/scsi/
DNCR5380.c348 } phases[] __maybe_unused = { variable
459 …for (i = 0; (phases[i].value != PHASE_UNKNOWN) && (phases[i].value != (status & PHASE_MASK)); ++i); in NCR5380_print_phase()
460 printk("scsi%d : phase %s\n", instance->host_no, phases[i].name); in NCR5380_print_phase()
Datari_NCR5380.c545 } phases[] = { variable
569 for (i = 0; (phases[i].value != PHASE_UNKNOWN) && in NCR5380_print_phase()
570 (phases[i].value != (status & PHASE_MASK)); ++i) in NCR5380_print_phase()
572 printk(KERN_DEBUG "scsi%d: phase %s\n", HOSTNO, phases[i].name); in NCR5380_print_phase()
Dsym53c416.c200 enum phases enum
/drivers/scsi/aic7xxx/
Daic7xxx.seq475 * Now determine what phases the host wants us
599 * Data phases on the bus are from the
656 * Main loop for information transfer phases. Wait for the
921 * As a target, we control the phases,
1344 * For data-in phases, wait for any pending acks from the
1346 * send Ignore Wide Residue messages for data-in phases.
Daic7xxx.reg130 * Possible phases in SCSISIGI
161 * Possible phases to write into SCSISIG0
Daic79xx.seq845 * Main loop for information transfer phases. Wait for the
1754 * For data-in phases, wait for any pending acks from the
1756 * send Ignore Wide Residue messages for data-in phases.
2121 * phases that are typically caused by CRC errors in status packet
Daic79xx.reg1745 * Possible phases to write into SCSISIG0
1776 * Possible phases in SCSISIGI