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Searched refs:pipeconf (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c593 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
700 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
702 pipeconf &= ~(PIPE_BPC_MASK); in cdv_intel_crtc_mode_set()
706 pipeconf |= PIPE_8BPC; in cdv_intel_crtc_mode_set()
709 pipeconf |= PIPE_6BPC; in cdv_intel_crtc_mode_set()
712 pipeconf |= PIPE_10BPC; in cdv_intel_crtc_mode_set()
715 pipeconf |= PIPE_8BPC; in cdv_intel_crtc_mode_set()
721 pipeconf |= PIPE_8BPC; in cdv_intel_crtc_mode_set()
723 pipeconf |= PIPE_6BPC; in cdv_intel_crtc_mode_set()
725 pipeconf |= PIPE_8BPC; in cdv_intel_crtc_mode_set()
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Dpsb_intel_display.c116 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
202 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
213 pipeconf |= PIPEACONF_ENABLE; in psb_intel_crtc_mode_set()
292 REG_WRITE(map->conf, pipeconf); in psb_intel_crtc_mode_set()
Doaktrail_hdmi.c281 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
361 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
362 pipeconf |= PIPEACONF_ENABLE; in oaktrail_crtc_hdmi_mode_set()
364 REG_WRITE(pipeconf_reg, pipeconf); in oaktrail_crtc_hdmi_mode_set()
367 REG_WRITE(PCH_PIPEBCONF, pipeconf); in oaktrail_crtc_hdmi_mode_set()
Dmdfld_intel_display.c311 u32 pipeconf = dev_priv->pipeconf[pipe]; in mdfld_crtc_dpms() local
375 REG_WRITE(map->conf, pipeconf); in mdfld_crtc_dpms()
858 dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */ in mdfld_crtc_mode_set()
1013 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); in mdfld_crtc_mode_set()
Doaktrail_crtc.c380 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in oaktrail_crtc_mode_set() local
494 pipeconf = REG_READ(map->conf); in oaktrail_crtc_mode_set()
585 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); in oaktrail_crtc_mode_set()
Dmdfld_dsi_dpi.c826 u32 pipeconf, dspcntr; in mdfld_dsi_dpi_mode_set() local
833 pipeconf = dev_priv->pipeconf[pipe]; in mdfld_dsi_dpi_mode_set()
907 REG_WRITE(pipeconf_reg, pipeconf); in mdfld_dsi_dpi_mode_set()
Dpsb_drv.h602 u32 pipeconf[3]; member
/drivers/gpu/drm/i915/
Dintel_crt.c522 uint32_t pipeconf = I915_READ(pipeconf_reg); in intel_crt_load_detect() local
523 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); in intel_crt_load_detect()
533 I915_WRITE(pipeconf_reg, pipeconf); in intel_crt_load_detect()
Dintel_display.c7836 uint32_t pipeconf; in i9xx_set_pipeconf() local
7838 pipeconf = 0; in i9xx_set_pipeconf()
7842 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
7845 pipeconf |= PIPECONF_DOUBLE_WIDE; in i9xx_set_pipeconf()
7851 pipeconf |= PIPECONF_DITHER_EN | in i9xx_set_pipeconf()
7856 pipeconf |= PIPECONF_6BPC; in i9xx_set_pipeconf()
7859 pipeconf |= PIPECONF_8BPC; in i9xx_set_pipeconf()
7862 pipeconf |= PIPECONF_10BPC; in i9xx_set_pipeconf()
7873 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; in i9xx_set_pipeconf()
7882 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; in i9xx_set_pipeconf()
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