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Searched refs:pll_con0 (Results 1 – 1 of 1) sorted by relevance

/drivers/clk/samsung/
Dclk-pll.c252 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; in samsung_pll36xx_recalc_rate() local
256 pll_con0 = __raw_readl(pll->con_reg); in samsung_pll36xx_recalc_rate()
258 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; in samsung_pll36xx_recalc_rate()
259 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; in samsung_pll36xx_recalc_rate()
260 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; in samsung_pll36xx_recalc_rate()
271 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) in samsung_pll36xx_mpk_change() argument
275 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; in samsung_pll36xx_mpk_change()
276 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; in samsung_pll36xx_mpk_change()
287 u32 tmp, pll_con0, pll_con1; in samsung_pll36xx_set_rate() local
297 pll_con0 = __raw_readl(pll->con_reg); in samsung_pll36xx_set_rate()
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