Searched refs:pll_con1 (Results 1 – 1 of 1) sorted by relevance
| /drivers/clk/samsung/ |
| D | clk-pll.c | 252 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; in samsung_pll36xx_recalc_rate() local
257 pll_con1 = __raw_readl(pll->con_reg + 4); in samsung_pll36xx_recalc_rate()
261 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK); in samsung_pll36xx_recalc_rate()
271 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) in samsung_pll36xx_mpk_change() argument
277 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; in samsung_pll36xx_mpk_change()
287 u32 tmp, pll_con0, pll_con1; in samsung_pll36xx_set_rate() local
298 pll_con1 = __raw_readl(pll->con_reg + 4); in samsung_pll36xx_set_rate()
300 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { in samsung_pll36xx_set_rate()
321 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); in samsung_pll36xx_set_rate()
322 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; in samsung_pll36xx_set_rate()
[all …]
|