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Searched refs:readl (Results 1 – 25 of 1229) sorted by relevance

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/drivers/net/ethernet/stmicro/stmmac/
Dmmc_core.c137 u32 value = readl(ioaddr + MMC_CNTRL); in dwmac_mmc_ctrl()
162 mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB); in dwmac_mmc_read()
163 mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB); in dwmac_mmc_read()
164 mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G); in dwmac_mmc_read()
165 mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G); in dwmac_mmc_read()
166 mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB); in dwmac_mmc_read()
168 readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB); in dwmac_mmc_read()
170 readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB); in dwmac_mmc_read()
172 readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB); in dwmac_mmc_read()
174 readl(ioaddr + MMC_TX_512_TO_1023_OCTETS_GB); in dwmac_mmc_read()
[all …]
Dstmmac_hwtstamp.c38 u32 value = readl(ioaddr + PTP_TCR); in stmmac_config_sub_second_increment()
62 value = readl(ioaddr + PTP_TCR); in stmmac_init_systime()
69 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSINIT)) in stmmac_init_systime()
86 value = readl(ioaddr + PTP_TCR); in stmmac_config_addend()
93 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG)) in stmmac_config_addend()
113 value = readl(ioaddr + PTP_TCR); in stmmac_adjust_systime()
120 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT)) in stmmac_adjust_systime()
134 ns = readl(ioaddr + PTP_STNSR); in stmmac_get_systime()
136 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL; in stmmac_get_systime()
Ddwmac_lib.c47 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
54 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
148 u32 intr_status = readl(ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
189 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt()
216 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
219 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()
240 u32 value = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
256 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
[all …]
/drivers/video/fbdev/mbx/
Dmbxdebugfs.c35 s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG)); in sysconf_read_file()
36 s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE)); in sysconf_read_file()
37 s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL)); in sysconf_read_file()
38 s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG)); in sysconf_read_file()
39 s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST)); in sysconf_read_file()
51 s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL)); in gsctl_read_file()
52 s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL)); in gsctl_read_file()
53 s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE)); in gsctl_read_file()
54 s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE)); in gsctl_read_file()
55 s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTRL)); in gsctl_read_file()
[all …]
/drivers/media/platform/s5p-jpeg/
Djpeg-hw-s5p.c25 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
29 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
48 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
63 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_proc_mode()
78 reg = readl(regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode()
86 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK; in s5p_jpeg_get_subsampling_mode()
93 reg = readl(regs + S5P_JPGDRI_U); in s5p_jpeg_dri()
98 reg = readl(regs + S5P_JPGDRI_L); in s5p_jpeg_dri()
108 reg = readl(regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl()
118 reg = readl(regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac()
[all …]
Djpeg-hw-exynos4.c23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
63 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_img_fmt()
137 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_enc_out_fmt()
170 reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; in exynos4_jpeg_set_interrupt()
173 reg = readl(base + EXYNOS4_INT_EN_REG) & in exynos4_jpeg_set_interrupt()
183 int_status = readl(base + EXYNOS4_INT_STATUS_REG); in exynos4_jpeg_get_int_status()
192 fifo_status = readl(base + EXYNOS4_FIFO_STATUS_REG); in exynos4_jpeg_get_fifo_status()
201 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; in exynos4_jpeg_set_huf_table_enable()
215 reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); in exynos4_jpeg_set_sys_int_enable()
[all …]
Djpeg-hw-exynos3250.c31 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
41 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
76 reg = readl(regs + EXYNOS3250_JPGCMOD) & in exynos3250_jpeg_input_raw_fmt()
127 reg = readl(regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16()
143 reg = readl(regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode()
165 reg = readl(regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode()
173 return readl(regs + EXYNOS3250_JPGMOD) & in exynos3250_jpeg_get_subsampling_mode()
189 reg = readl(regs + EXYNOS3250_QHTBL); in exynos3250_jpeg_qtbl()
200 reg = readl(regs + EXYNOS3250_QHTBL); in exynos3250_jpeg_htbl_ac()
[all …]
/drivers/video/fbdev/exynos/
Dexynos_mipi_dsi_lowlevel.c36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & in exynos_mipi_dsi_get_sw_reset_release()
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_read_interrupt_mask()
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by()
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & in exynos_mipi_dsi_set_main_disp_resol()
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & in exynos_mipi_dsi_set_main_disp_vporch()
169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & in exynos_mipi_dsi_set_main_disp_hporch()
[all …]
/drivers/gpu/drm/exynos/
Dexynos_dp_reg.c32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
182 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_get_pll_lock_status()
194 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
213 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
224 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
[all …]
/drivers/scsi/bfa/
Dbfa_ioc_ct.c67 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
74 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
81 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
94 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
105 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
120 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
127 readl(ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
141 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
142 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
145 readl(ioc->ioc_regs.err_set); in bfa_ioc_ct_notify_fail()
[all …]
/drivers/ata/
Dahci_xgene.c108 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ in xgene_ahci_init_memram()
110 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { in xgene_ahci_init_memram()
176 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
178 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
216 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
239 return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 && in xgene_ahci_is_memram_inited()
240 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF); in xgene_ahci_is_memram_inited()
287 val = readl(mmio + PORTCFG); in xgene_ahci_set_phy_cfg()
290 readl(mmio + PORTCFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
293 readl(mmio + PORTPHY1CFG); /* Force a barrier */ in xgene_ahci_set_phy_cfg()
[all …]
Dsata_sx4.c509 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_dma_prep()
544 readl(dimm_mmio); /* MMIO PCI posting flush */ in pdc20621_nodata_prep()
577 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
580 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ in __pdc20621_push_hdma()
630 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio)); in pdc20621_dump_hdma()
631 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4)); in pdc20621_dump_hdma()
632 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8)); in pdc20621_dump_hdma()
633 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12)); in pdc20621_dump_hdma()
670 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in pdc20621_packet_start()
674 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); in pdc20621_packet_start()
[all …]
/drivers/net/ethernet/brocade/bna/
Dbfa_ioc_ct.c133 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
145 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); in bfa_ioc_ct_firmware_lock()
186 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
202 readl(ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
203 readl(ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
385 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
397 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
408 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
435 r32 = readl(ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
458 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
[all …]
/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_core.c29 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
37 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
57 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
77 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); in sxgbe_core_host_irq_status()
108 high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
109 low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_get_umac_addr()
124 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx()
136 rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx()
146 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
153 return readl(ioaddr + (SXGBE_CORE_HW_FEA_REG(feature_index))); in sxgbe_get_hw_feature()
[all …]
Dsxgbe_mtl.c28 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
71 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
83 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize()
92 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_enable_txqueue()
101 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_disable_txqueue()
111 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_active()
122 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_enable()
132 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_deactive()
143 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_enable()
153 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fep_disable()
[all …]
/drivers/i2c/busses/
Di2c-pxa.c283 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_show_state()
298 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), in i2c_pxa_scream_blue_murder()
299 readl(_ISR(i2c))); in i2c_pxa_scream_blue_murder()
322 return !(readl(_ICR(i2c)) & ICR_SCLE); in i2c_pxa_is_slavemode()
334 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { in i2c_pxa_abort()
335 unsigned long icr = readl(_ICR(i2c)); in i2c_pxa_abort()
348 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), in i2c_pxa_abort()
356 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { in i2c_pxa_wait_bus_not_busy()
357 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) in i2c_pxa_wait_bus_not_busy()
377 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); in i2c_pxa_wait_master()
[all …]
/drivers/phy/
Dphy-mt65xx-usb3.c137 tmp = readl(port_base + U3P_U2PHYDTM0); in phy_instance_init()
142 tmp = readl(port_base + U3P_U2PHYDTM1); in phy_instance_init()
147 tmp = readl(port_base + U3P_U2PHYACR4); in phy_instance_init()
151 tmp = readl(port_base + U3P_USBPHYACR2); in phy_instance_init()
155 tmp = readl(port_base + U3D_U2PHYDCR0); in phy_instance_init()
159 tmp = readl(port_base + U3D_U2PHYDCR0); in phy_instance_init()
163 tmp = readl(port_base + U3P_U2PHYDTM0); in phy_instance_init()
169 tmp = readl(port_base + U3P_USBPHYACR6); in phy_instance_init()
173 tmp = readl(port_base + U3P_U3PHYA_DA_REG0); in phy_instance_init()
178 tmp = readl(port_base + U3P_U3_PHYA_REG9); in phy_instance_init()
[all …]
/drivers/media/platform/exynos4-is/
Dfimc-lite-reg.c28 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
33 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
45 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq()
52 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_get_interrupt_source()
59 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end()
80 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask()
88 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start()
95 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop()
106 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern()
147 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format()
[all …]
/drivers/usb/phy/
Dphy-tegra-usb.c212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd()
237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; in set_phcd()
268 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
303 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
319 if ((readl(reg) & mask) == result) in utmi_wait_register()
333 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
339 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
355 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_enable()
[all …]
/drivers/usb/early/
Dehci-dbgp.c81 dbgp_printk(" Debug control: %08x", readl(&ehci_debug->control)); in dbgp_ehci_status()
82 dbgp_printk(" ehci cmd : %08x", readl(&ehci_regs->command)); in dbgp_ehci_status()
84 readl(&ehci_regs->configured_flag)); in dbgp_ehci_status()
85 dbgp_printk(" ehci status : %08x", readl(&ehci_regs->status)); in dbgp_ehci_status()
87 readl(&ehci_regs->port_status[dbgp_phys_port - 1])); in dbgp_ehci_status()
167 ctrl = readl(&ehci_debug->control); in dbgp_wait_until_complete()
208 pids = readl(&ehci_debug->pids); in dbgp_wait_until_done()
262 lo = readl(&ehci_debug->data03); in dbgp_get_data()
263 hi = readl(&ehci_debug->data47); in dbgp_get_data()
282 pids = readl(&ehci_debug->pids); in dbgp_bulk_write()
[all …]
/drivers/tty/serial/
Dimx.c296 ucr->ucr1 = readl(port->membase + UCR1); in imx_port_ucrs_save()
297 ucr->ucr2 = readl(port->membase + UCR2); in imx_port_ucrs_save()
298 ucr->ucr3 = readl(port->membase + UCR3); in imx_port_ucrs_save()
371 temp = readl(port->membase + UCR1); in imx_stop_tx()
376 readl(port->membase + USR2) & USR2_TXDC) { in imx_stop_tx()
377 temp = readl(port->membase + UCR2); in imx_stop_tx()
384 temp = readl(port->membase + UCR4); in imx_stop_tx()
407 temp = readl(sport->port.membase + UCR2); in imx_stop_rx()
411 temp = readl(sport->port.membase + UCR1); in imx_stop_rx()
449 temp = readl(sport->port.membase + UCR1); in imx_transmit_buffer()
[all …]
Dnetx-serial.c121 val = readl(port->membase + UART_CR); in netx_stop_tx()
128 val = readl(port->membase + UART_CR); in netx_stop_rx()
135 val = readl(port->membase + UART_CR); in netx_enable_ms()
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF)); in netx_transmit_buffer()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); in netx_start_tx()
175 if (!(readl(port->membase + UART_FR) & FR_TXFF)) in netx_start_tx()
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT; in netx_tx_empty()
203 while (!(readl(port->membase + UART_FR) & FR_RXFE)) { in netx_rxint()
204 rx = readl(port->membase + UART_DR); in netx_rxint()
207 status = readl(port->membase + UART_SR); in netx_rxint()
[all …]
/drivers/net/ethernet/agere/
Det131x.c757 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
760 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_enable()
775 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
778 csr = readl(&adapter->regs->rxdma.csr); in et131x_rx_dma_disable()
873 ctl = readl(&adapter->regs->txmac.ctl); in et1310_config_mac_regs2()
874 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
875 cfg2 = readl(&mac->cfg2); in et1310_config_mac_regs2()
876 ifctrl = readl(&mac->if_ctrl); in et1310_config_mac_regs2()
920 cfg1 = readl(&mac->cfg1); in et1310_config_mac_regs2()
940 u32 pmcsr = readl(&adapter->regs->global.pm_csr); in et1310_in_phy_coma()
[all …]
/drivers/block/
Dcciss.h227 readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); in SA5_submit_command()
244 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
250 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()
264 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
270 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()
280 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
285 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
308 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); in SA5_completed()
334 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
341 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); in SA5_performant_completed()
[all …]
/drivers/clk/mediatek/
Dclk-pll.c63 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
96 pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; in mtk_pll_set_rate_regs()
99 val = readl(pll->pd_addr); in mtk_pll_set_rate_regs()
106 val = readl(pll->pcw_addr); in mtk_pll_set_rate_regs()
115 con1 = readl(pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs()
192 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; in mtk_pll_recalc_rate()
195 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; in mtk_pll_recalc_rate()
218 r = readl(pll->pwr_addr) | CON0_PWR_ON; in mtk_pll_prepare()
222 r = readl(pll->pwr_addr) & ~CON0_ISO_EN; in mtk_pll_prepare()
226 r = readl(pll->base_addr + REG_CON0); in mtk_pll_prepare()
[all …]

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