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Searched refs:sh_mem_bases (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdkfd/
Dkfd_device_queue_manager_cik.c123 qpd->sh_mem_bases = SHARED_BASE(temp); in register_process_cik()
127 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in register_process_cik()
131 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in register_process_cik()
Dkfd_device_queue_manager_vi.c132 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT; in register_process_vi()
137 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in register_process_vi()
143 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in register_process_vi()
Dkfd_pm4_headers_vi.h166 uint32_t sh_mem_bases; member
Dkfd_pm4_headers.h167 uint32_t sh_mem_bases; member
Dkfd_packet_manager.c175 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_create_map_process()
Dkfd_priv.h432 uint32_t sh_mem_bases; member
Dkfd_device_queue_manager.c91 qpd->sh_mem_bases); in program_sh_mem_settings()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v8.c52 uint32_t sh_mem_bases);
164 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
173 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
Damdgpu_amdkfd_gfx_v7.c91 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
203 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
212 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
Dgfx_v7_0.c2027 uint32_t sh_mem_bases; in gmc_v7_0_init_compute_vmid() local
2035 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gmc_v7_0_init_compute_vmid()
2046 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gmc_v7_0_init_compute_vmid()
Dgfx_v8_0.c2860 uint32_t sh_mem_bases; in gfx_v8_0_init_compute_vmid() local
2868 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v8_0_init_compute_vmid()
2884 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v8_0_init_compute_vmid()
/drivers/gpu/drm/amd/include/
Dkgd_kfd_interface.h140 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
/drivers/gpu/drm/radeon/
Dradeon_kfd.c69 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
384 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
391 write_register(kgd, SH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
Dcik.c5791 uint32_t sh_mem_bases, sh_mem_config; in cik_pcie_init_compute_vmid() local
5793 sh_mem_bases = 0x6000 | 0x6000 << 16; in cik_pcie_init_compute_vmid()
5804 WREG32(SH_MEM_BASES, sh_mem_bases); in cik_pcie_init_compute_vmid()