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Searched refs:skl_ddb_entry (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
Di915_drv.h1571 struct skl_ddb_entry { struct
1575 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) in skl_ddb_entry_size() argument
1580 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, in skl_ddb_entry_equal()
1581 const struct skl_ddb_entry *e2) in skl_ddb_entry_equal()
1590 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1591 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1592 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
Dintel_pm.c2777 struct skl_ddb_entry *alloc /* out */) in skl_ddb_get_pipe_allocation_limits()
2820 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) in skl_ddb_entry_init_from_hw()
2907 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; in skl_allocate_pipe_ddb()
3364 const struct skl_ddb_entry *entry) in skl_ddb_entry_write()
3628 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); in skl_clear_wm()
3630 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); in skl_clear_wm()
3632 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); in skl_clear_wm()
3634 sizeof(struct skl_ddb_entry)); in skl_clear_wm()
Di915_debugfs.c3139 struct skl_ddb_entry *entry; in i915_ddb_info()
Dintel_display.c12673 struct skl_ddb_entry *hw_entry, *sw_entry; in check_wm_state()