| /drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 37 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
43 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
106 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
146 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
181 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
209 if (spll->reference_div < 2) in radeon_get_clock_info()
210 spll->reference_div = in radeon_get_clock_info()
215 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
228 spll->reference_freq = 1432; in radeon_get_clock_info()
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| D | radeon_combios.c | 736 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
763 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
764 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
765 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
766 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
769 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
770 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
773 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
774 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
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| D | radeon_atombios.c | 1144 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1197 spll->reference_freq = in radeon_atom_get_clock_info()
1200 spll->reference_freq = in radeon_atom_get_clock_info()
1202 spll->reference_div = 0; in radeon_atom_get_clock_info()
1204 spll->pll_out_min = in radeon_atom_get_clock_info()
1206 spll->pll_out_max = in radeon_atom_get_clock_info()
1210 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1212 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1214 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1217 spll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
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| D | rv6xx_dpm.c | 164 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
429 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
552 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
841 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
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| D | rv740_dpm.c | 132 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
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| D | rs780_dpm.c | 990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
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| D | rv730_dpm.c | 52 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
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| D | radeon_uvd.c | 920 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers()
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| D | radeon_kms.c | 331 *value = rdev->clock.spll.reference_freq * 10; in radeon_info_ioctl()
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| D | rv770.c | 792 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_get_xclk()
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| D | ci_dpm.c | 1966 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
2986 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3145 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
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| D | r600.c | 194 return rdev->clock.spll.reference_freq; in r600_get_xclk()
221 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
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| D | rv770_dpm.c | 501 u32 reference_clock = rdev->clock.spll.reference_freq; in rv770_populate_sclk_value()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
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| D | nv50.c | 474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
483 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 556 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
602 spll->reference_freq = in amdgpu_atombios_get_clock_info()
604 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
606 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
608 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
612 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
613 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
615 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
617 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
620 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
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| D | vi.c | 290 u32 reference_clock = adev->clock.spll.reference_freq; in vi_get_xclk()
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| D | cik.c | 839 u32 reference_clock = adev->clock.spll.reference_freq; in cik_get_xclk()
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| D | amdgpu.h | 377 struct amdgpu_pll spll; member
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| D | ci_dpm.c | 2094 u32 ref_clock = adev->clock.spll.reference_freq; in ci_program_display_gap()
3122 table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
3283 u32 reference_clock = adev->clock.spll.reference_freq; in ci_calculate_sclk_params()
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| /drivers/gpu/drm/i915/ |
| D | intel_ddi.c | 1299 struct intel_shared_dpll_config *spll = in hsw_ddi_pll_select() local
1302 if (spll->crtc_mask && in hsw_ddi_pll_select()
1303 WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) in hsw_ddi_pll_select()
1307 spll->hw_state.spll = crtc_state->dpll_hw_state.spll; in hsw_ddi_pll_select()
1308 spll->crtc_mask |= 1 << intel_crtc->pipe; in hsw_ddi_pll_select()
2472 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); in hsw_ddi_spll_enable()
2522 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
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| D | intel_crt.c | 266 pipe_config->dpll_hw_state.spll = in intel_crt_compute_config()
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| D | i915_drv.h | 373 uint32_t spll; member
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| /drivers/clk/imx/ |
| D | clk-imx31.c | 51 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
87 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
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| /drivers/clk/samsung/ |
| D | clk-exynos5420.c | 146 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator
1246 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
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