| /drivers/gpu/drm/nouveau/ |
| D | nouveau_dma.h | 111 BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) in BEGIN_NV04() argument
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NV04()
117 BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) in BEGIN_NI04() argument
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NI04()
123 BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) in BEGIN_NVC0() argument
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NVC0()
129 BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) in BEGIN_NIC0() argument
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NIC0()
135 BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) in BEGIN_IMC0() argument
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_IMC0()
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| /drivers/gpu/drm/nouveau/nvkm/engine/sw/ |
| D | chan.h | 19 bool (*mthd)(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data);
25 bool nvkm_sw_chan_mthd(struct nvkm_sw_chan *, int subc, u32 mthd, u32 data);
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| D | chan.c | 33 nvkm_sw_chan_mthd(struct nvkm_sw_chan *chan, int subc, u32 mthd, u32 data) in nvkm_sw_chan_mthd() argument
43 return chan->func->mthd(chan, subc, mthd, data); in nvkm_sw_chan_mthd()
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| D | base.c | 30 nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data) in nvkm_sw_mthd() argument
39 handled = nvkm_sw_chan_mthd(chan, subc, mthd, data); in nvkm_sw_mthd()
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| D | nv04.c | 87 nv04_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) in nv04_sw_chan_mthd() argument
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| D | gf100.c | 57 gf100_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) in gf100_sw_chan_mthd() argument
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| D | nv50.c | 62 nv50_sw_chan_mthd(struct nvkm_sw_chan *base, int subc, u32 mthd, u32 data) in nv50_sw_chan_mthd() argument
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| /drivers/gpu/drm/nouveau/nvkm/engine/sec/ |
| D | g98.c | 50 u32 subc = (addr & 0x3800) >> 11; in g98_sec_intr() local
60 subc, mthd, data); in g98_sec_intr()
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| D | gt215.c | 51 u32 subc = (addr & 0x3800) >> 11; in gt215_ce_intr() local
61 subc, mthd, data); in gt215_ce_intr()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv50.c | 421 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_trap_handler() local
434 chid, inst, name, subc, class, mthd, in nv50_gr_trap_handler()
449 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_trap_handler() local
460 subc, class, mthd, data, addr); in nv50_gr_trap_handler()
627 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_intr() local
667 subc, class, mthd, data); in nv50_gr_intr()
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| D | nv20.c | 190 u32 subc = (addr & 0x00070000) >> 16; in nv20_gr_intr() local
193 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; in nv20_gr_intr()
212 subc, class, mthd, data); in nv20_gr_intr()
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| D | nv40.c | 243 u32 subc = (addr & 0x00070000) >> 16; in nv40_gr_intr() local
246 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; in nv40_gr_intr()
280 subc, class, mthd, data); in nv40_gr_intr()
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| D | nv04.c | 447 int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; in nv04_gr_set_ctx1() local
456 nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc << 2), tmp); in nv04_gr_set_ctx1()
1282 u32 subc = (addr & 0x0000e000) >> 13; in nv04_gr_intr() local
1285 u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; in nv04_gr_intr()
1321 subc, class, mthd, data); in nv04_gr_intr()
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| D | gf100.c | 1167 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_ctxctl_isr() local
1173 subc, class, mthd, data); in gf100_gr_ctxctl_isr()
1208 u32 subc = (addr & 0x00070000) >> 16; in gf100_gr_intr() local
1221 if (device->card_type < NV_E0 || subc < 4) in gf100_gr_intr()
1222 class = nvkm_rd32(device, 0x404200 + (subc * 4)); in gf100_gr_intr()
1239 chid, inst << 12, name, subc, in gf100_gr_intr()
1249 chid, inst << 12, name, subc, class, mthd, data); in gf100_gr_intr()
1260 name, subc, class, mthd, data); in gf100_gr_intr()
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| D | nv10.c | 1091 u32 subc = (addr & 0x00070000) >> 16; in nv10_gr_intr() local
1094 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; in nv10_gr_intr()
1129 subc, class, mthd, data); in nv10_gr_intr()
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | nv04.c | 111 const int subc = (addr & 0x0000e000) >> 13; in nv04_fifo_swmthd() local
113 const u32 mask = 0x0000000f << (subc * 4); in nv04_fifo_swmthd()
125 handled = nvkm_sw_mthd(sw, chid, subc, mthd, data); in nv04_fifo_swmthd()
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| D | gf100.c | 367 u32 subc = (addr & 0x00070000) >> 16; in gf100_fifo_intr_pbdma() local
376 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) in gf100_fifo_intr_pbdma()
388 subc, mthd, data); in gf100_fifo_intr_pbdma()
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| D | gk104.c | 459 u32 subc = (addr & 0x00070000) >> 16; in gk104_fifo_intr_pbdma_0() local
468 if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data)) in gk104_fifo_intr_pbdma_0()
481 subc, mthd, data); in gk104_fifo_intr_pbdma_0()
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| /drivers/gpu/drm/nouveau/include/nvkm/engine/ |
| D | sw.h | 12 bool nvkm_sw_mthd(struct nvkm_sw *sw, int chid, int subc, u32 mthd, u32 data);
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| /drivers/gpu/drm/i2c/ |
| D | ch7006_mode.c | 106 subc, scale, scale_mask, norm_mask, e_hd, e_vd) { \ argument
128 .subc_coeff = subc * fixed1, \
136 subc, scale, scale_mask, norm_mask) \ argument
137 __MODE(f, hd, vd, ht, vt, hsynp, vsynp, subc, scale, \
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