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Searched refs:tpc_total (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dctxgk104.c899 for (tpc = 0; tpc < gr->tpc_total; tpc++) { in gk104_grctx_generate_r418bb8()
913 ntpcv = gr->tpc_total; in gk104_grctx_generate_r418bb8()
926 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
932 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
939 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
984 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk104_grctx_generate_main()
Dctxgf100.c1062 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); in gf100_grctx_generate_attrib()
1131 for (tpc = 0; tpc < gr->tpc_total; tpc++) { in gf100_grctx_generate_r4060a8()
1156 for (tpc = 0; tpc < gr->tpc_total; tpc++) { in gf100_grctx_generate_r418bb8()
1170 ntpcv = gr->tpc_total; in gf100_grctx_generate_r418bb8()
1183 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf100_grctx_generate_r418bb8()
1189 nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | in gf100_grctx_generate_r418bb8()
1196 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf100_grctx_generate_r418bb8()
1216 a = (i * (gr->tpc_total - 1)) / 32; in gf100_grctx_generate_r406800()
Dgk20a.c186 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gk20a_gr_init()
218 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { in gk20a_gr_init()
236 gr->tpc_total); in gk20a_gr_init()
261 nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); in gk20a_gr_init()
Dctxgm204.c952 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gm204_grctx_generate_405b60()
964 for (gpc = -1, i = 0; i < gr->tpc_total; i++) { in gm204_grctx_generate_405b60()
1009 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm204_grctx_generate_main()
Dgm204.c242 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gm204_gr_init()
269 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { in gm204_gr_init()
287 gr->tpc_total); in gm204_gr_init()
Dgk104.c184 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gk104_gr_init()
205 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { in gk104_gr_init()
223 gr->tpc_total); in gk104_gr_init()
Dctxgf108.c740 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); in gf108_grctx_generate_attrib()
744 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf108_grctx_generate_attrib()
Dgm107.c314 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gm107_gr_init()
334 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { in gm107_gr_init()
352 gr->tpc_total); in gm107_gr_init()
Dctxgm107.c905 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); in gm107_grctx_generate_attrib()
908 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gm107_grctx_generate_attrib()
985 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm107_grctx_generate_main()
Dctxgf117.c192 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); in gf117_grctx_generate_attrib()
196 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf117_grctx_generate_attrib()
Dctxgk20a.c54 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
Dgf100.c823 cfg |= (u32)gr->tpc_total << 8; in gf100_gr_units()
1548 gr->tpc_total += gr->tpc_nr[i]; in gf100_gr_oneinit()
1561 if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ in gf100_gr_oneinit()
1564 if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ in gf100_gr_oneinit()
1567 if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ in gf100_gr_oneinit()
1722 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init()
1742 for (i = 0, gpc = -1; i < gr->tpc_total; i++) { in gf100_gr_init()
1760 gr->tpc_total); in gf100_gr_init()
Dctxgm20b.c64 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
Dgf100.h98 u8 tpc_total; member