| /drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 897 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
909 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
942 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
953 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1457 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1691 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1694 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1931 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
2017 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2042 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | sumo_dpm.c | 825 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
841 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
859 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1415 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1418 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 911 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
926 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
941 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
953 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | rv770_dpm.c | 1439 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1446 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1456 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1463 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2154 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2157 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2163 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2440 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2484 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1519 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.h | 69 u32 vclk; member
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| D | radeon_asic.h | 411 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
477 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
534 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
748 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
786 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | rv770.c | 45 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
47 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
54 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
61 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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| D | ni_dpm.c | 3515 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3523 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3533 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3541 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3904 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3907 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3910 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
4288 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4316 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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| D | kv_dpm.c | 835 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
840 (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk); in kv_populate_uvd_table()
845 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
2221 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2594 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2597 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2854 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
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| D | radeon.h | 1352 u32 vclk; member
1438 u32 vclk; member
1701 unsigned vclk, unsigned dclk,
1966 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| /drivers/video/fbdev/via/ |
| D | vt1636.c | 200 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
224 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
241 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| D | chip.h | 155 u32 vclk; /*panel mode clock value */ member
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| /drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 53 struct clk *vclk; member
162 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
585 ret = clk_prepare_enable(ctx->vclk); in decon_enable()
616 clk_disable_unprepare(ctx->vclk); in decon_disable()
783 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
784 if (IS_ERR(ctx->vclk)) { in decon_probe()
786 ret = PTR_ERR(ctx->vclk); in decon_probe()
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| /drivers/video/fbdev/aty/ |
| D | aty128fb.c | 433 u32 vclk; member
1377 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1381 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1384 if (vclk > c.ppll_max) in aty128_var_to_pll()
1385 vclk = c.ppll_max; in aty128_var_to_pll()
1386 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1387 vclk = c.ppll_min/12; in aty128_var_to_pll()
1391 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1406 pll->vclk = vclk; in aty128_var_to_pll()
1410 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
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| D | radeon_base.c | 585 unsigned long long hz, vclk; in radeon_probe_pll_params() local
629 vclk = (long long)hTotal * (long long)vTotal * hz; in radeon_probe_pll_params()
681 vclk *= denom; in radeon_probe_pll_params()
682 do_div(vclk, 1000 * num); in radeon_probe_pll_params()
683 xtal = vclk; in radeon_probe_pll_params()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | cz_dpm.c | 270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in cz_parse_pplib_non_clock_info()
273 rps->vclk = 0; in cz_parse_pplib_non_clock_info()
521 u32 sclk, vclk, dclk, ecclk, tmp; in cz_dpm_debugfs_print_current_performance_level() local
544 vclk = uvd_table->entries[uvd_index].vclk; in cz_dpm_debugfs_print_current_performance_level()
546 seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk); in cz_dpm_debugfs_print_current_performance_level()
570 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in cz_dpm_print_power_state()
760 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in cz_dpm_upload_pptable_to_smu()
850 clock = table->entries[level].vclk; in cz_init_uvd_limit()
853 clock = table->entries[table->count - 1].vclk; in cz_init_uvd_limit()
1248 pi->video_start = new_rps->dclk || new_rps->vclk || in cz_apply_state_adjust_rules()
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| D | kv_dpm.c | 924 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
929 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
934 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
2315 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2691 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2694 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2921 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
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| D | vi.c | 1001 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1005 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in vi_set_uvd_clocks()
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| D | amdgpu.h | 1374 u32 vclk; member
1462 u32 vclk; member
1845 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
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| D | cik.c | 1513 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in cik_set_uvd_clocks() argument
1517 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); in cik_set_uvd_clocks()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 253 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| D | hw.h | 57 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
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| /drivers/video/fbdev/ |
| D | tridentfb.c | 1143 unsigned long vclk; in tridentfb_set_par() local
1303 vclk = PICOS2KHZ(info->var.pixclock); in tridentfb_set_par()
1309 vclk *= 2; in tridentfb_set_par()
1311 set_vclk(par, vclk); in tridentfb_set_par()
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