Searched refs:vddc_table (Results 1 – 7 of 7) sorted by relevance
579 if (vddc <= pi->vddc_table[i].vddc) { in rv770_populate_vddc_value()580 voltage->index = pi->vddc_table[i].vddc_index; in rv770_populate_vddc_value()1121 table->highSMIO[pi->vddc_table[i].vddc_index] = in rv770_populate_smc_vddc_table()1122 pi->vddc_table[i].high_smio; in rv770_populate_smc_vddc_table()1123 table->lowSMIO[pi->vddc_table[i].vddc_index] = in rv770_populate_smc_vddc_table()1124 cpu_to_be32(pi->vddc_table[i].low_smio); in rv770_populate_smc_vddc_table()1134 pi->vddc_table[i].vddc)); in rv770_populate_smc_vddc_table()1138 pi->vddc_table[i].vddc_index; in rv770_populate_smc_vddc_table()1252 pi->vddc_table[i].vddc = (u16)(min + i * step); in rv770_construct_vddc_table()1254 pi->vddc_table[i].vddc, in rv770_construct_vddc_table()[all …]
71 struct ci_single_dpm_table vddc_table; member
105 struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; member
3446 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()3482 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()3484 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()3486 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()3488 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()3763 struct radeon_clock_voltage_dependency_table *vddc_table = in ci_apply_disp_minimum_voltage_request() local3778 for (i = 0; i < vddc_table->count; i++) { in ci_apply_disp_minimum_voltage_request()3779 if (requested_voltage <= vddc_table->entries[i].v) { in ci_apply_disp_minimum_voltage_request()3780 requested_voltage = vddc_table->entries[i].v; in ci_apply_disp_minimum_voltage_request()
693 struct amdgpu_clock_voltage_dependency_table *vddc_table = in cz_dpm_upload_pptable_to_smu() local715 if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS || in cz_dpm_upload_pptable_to_smu()728 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0; in cz_dpm_upload_pptable_to_smu()730 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0; in cz_dpm_upload_pptable_to_smu()
72 struct ci_single_dpm_table vddc_table; member
3582 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()3618 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()3620 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()3622 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()3624 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()3899 struct amdgpu_clock_voltage_dependency_table *vddc_table = in ci_apply_disp_minimum_voltage_request() local3914 for (i = 0; i < vddc_table->count; i++) { in ci_apply_disp_minimum_voltage_request()3915 if (requested_voltage <= vddc_table->entries[i].v) { in ci_apply_disp_minimum_voltage_request()3916 requested_voltage = vddc_table->entries[i].v; in ci_apply_disp_minimum_voltage_request()