Searched refs:vlv_cck_read (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/drm/i915/ |
| D | intel_dsi_pll.c | 263 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_enable_dsi_pll()
267 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & in vlv_enable_dsi_pll()
288 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_disable_dsi_pll()
338 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in vlv_get_dsi_pclk()
339 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); in vlv_get_dsi_pclk()
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| D | intel_sideband.c | 146 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg) in vlv_cck_read() function
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| D | i915_drv.h | 3425 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
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| D | intel_display.c | 143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & in valleyview_get_vco()
160 val = vlv_cck_read(dev_priv, reg); in vlv_get_cck_clock_hpll()
1178 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in assert_dsi_pll()
5899 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in valleyview_set_cdclk()
5904 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in valleyview_set_cdclk()
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| D | intel_pm.c | 5419 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); in cherryview_init_gt_powersave()
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