Home
last modified time | relevance | path

Searched refs:vmw_read (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/vmwgfx/
Dvmwgfx_drv.c492 width = vmw_read(dev_priv, SVGA_REG_WIDTH); in vmw_get_initial_size()
493 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); in vmw_get_initial_size()
666 svga_id = vmw_read(dev_priv, SVGA_REG_ID); in vmw_driver_load()
673 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); in vmw_driver_load()
680 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); in vmw_driver_load()
681 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); in vmw_driver_load()
682 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); in vmw_driver_load()
683 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); in vmw_driver_load()
689 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); in vmw_driver_load()
691 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); in vmw_driver_load()
[all …]
Dvmwgfx_fifo.c54 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
120 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); in vmw_fifo_init()
121 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); in vmw_fifo_init()
122 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); in vmw_fifo_init()
124 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_fifo_init()
125 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_fifo_init()
126 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_fifo_init()
134 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); in vmw_fifo_init()
181 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) in vmw_fifo_release()
Dvmwgfx_kms.c1205 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) { in vmw_kms_write_svga()
1207 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); in vmw_kms_write_svga()
1219 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH); in vmw_kms_save_vga()
1220 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT); in vmw_kms_save_vga()
1221 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL); in vmw_kms_save_vga()
1224 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK); in vmw_kms_save_vga()
1232 vmw_priv->num_displays = vmw_read(vmw_priv, in vmw_kms_save_vga()
1241 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY); in vmw_kms_save_vga()
1242 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X); in vmw_kms_save_vga()
1243 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y); in vmw_kms_save_vga()
[all …]
Dvmwgfx_ioctl.c165 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_fill_compat_cap()
221 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_get_cap_3d_ioctl()
Dvmwgfx_irq.c67 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); in vmw_fifo_idle()
Dvmwgfx_fb.c652 fb_offset = vmw_read(vmw_priv, SVGA_REG_FB_OFFSET); in vmw_fb_init()
Dvmwgfx_drv.h568 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() function