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Searched refs:wptr (Results 1 – 25 of 65) sorted by relevance

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/drivers/media/usb/pvrusb2/
Dpvrusb2-debugifc.c69 const char *wptr; in debugifc_isolate_word() local
74 wptr = NULL; in debugifc_isolate_word()
82 wptr = buf; in debugifc_isolate_word()
87 *wstrPtr = wptr; in debugifc_isolate_word()
198 const char *wptr; in pvr2_debugifc_do1cmd() local
202 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
205 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
207 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
208 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
209 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
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/drivers/gpu/drm/amd/amdkfd/
Dkfd_interrupt.c111 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); in enqueue_ih_ring_entry() local
113 if ((rptr - wptr) % kfd->interrupt_ring_size == in enqueue_ih_ring_entry()
121 memcpy(kfd->interrupt_ring + wptr, ih_ring_entry, in enqueue_ih_ring_entry()
124 wptr = (wptr + kfd->device_info->ih_ring_entry_size) % in enqueue_ih_ring_entry()
127 atomic_set(&kfd->interrupt_ring_wptr, wptr); in enqueue_ih_ring_entry()
143 unsigned int wptr = atomic_read(&kfd->interrupt_ring_wptr); in dequeue_ih_ring_entry() local
146 if (rptr == wptr) in dequeue_ih_ring_entry()
Dkfd_kernel_queue.c208 uint32_t wptr, rptr; in acquire_packet_buffer() local
214 wptr = *kq->wptr_kernel; in acquire_packet_buffer()
219 pr_debug("wptr: %d\n", wptr); in acquire_packet_buffer()
222 available_size = (rptr - 1 - wptr + queue_size_dwords) % in acquire_packet_buffer()
235 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in acquire_packet_buffer()
236 while (wptr > 0) { in acquire_packet_buffer()
237 queue_address[wptr] = kq->nop_packet; in acquire_packet_buffer()
238 wptr = (wptr + 1) % queue_size_dwords; in acquire_packet_buffer()
242 *buffer_ptr = &queue_address[wptr]; in acquire_packet_buffer()
243 kq->pending_wptr = wptr + packet_size_in_dwords; in acquire_packet_buffer()
/drivers/net/ppp/
Dbsd_comp.c580 unsigned char *wptr; in bsd_compress() local
586 if (wptr) \ in bsd_compress()
588 *wptr++ = (unsigned char) (v); \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
644 *wptr++ = PPP_COMP; in bsd_compress()
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Dppp_deflate.c193 unsigned char *wptr; in z_compress() local
207 wptr = obuf; in z_compress()
212 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
213 wptr[1] = PPP_CONTROL(rptr); in z_compress()
214 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
215 wptr += PPP_HDRLEN; in z_compress()
216 put_unaligned_be16(state->seqno, wptr); in z_compress()
217 wptr += DEFLATE_OVHD; in z_compress()
219 state->strm.next_out = wptr; in z_compress()
/drivers/net/ethernet/tehuti/
Dtehuti.c172 f->wptr = 0; in bdx_fifo_init()
1116 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1124 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1125 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1127 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1136 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1173 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1181 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1182 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1184 f->m.wptr = delta; in bdx_recycle_skb()
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/drivers/gpu/drm/radeon/
Dradeon_ring.c84 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
125 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
173 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
211 ring->wptr = ring->wptr_old; in radeon_ring_undo()
308 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
468 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info() local
474 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info()
476 wptr, wptr); in radeon_debugfs_ring_info()
490 ring->wptr, ring->wptr); in radeon_debugfs_ring_info()
Dvce_v1_0.c97 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
99 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
Dni_dma.c111 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cayman_dma_set_wptr()
129 u32 next_rptr = ring->wptr + 4; in cayman_dma_ring_ib_execute()
142 while ((ring->wptr & 7) != 5) in cayman_dma_ring_ib_execute()
243 ring->wptr = 0; in cayman_dma_resume()
244 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); in cayman_dma_resume()
Dr600_dma.c89 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
167 ring->wptr = 0; in r600_dma_resume()
168 WREG32(DMA_RB_WPTR, ring->wptr << 2); in r600_dma_resume()
405 u32 next_rptr = ring->wptr + 4; in r600_dma_ring_ib_execute()
418 while ((ring->wptr & 7) != 5) in r600_dma_ring_ib_execute()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ring.c65 ring->ring_free_dw -= ring->wptr; in amdgpu_ring_free_size()
104 ring->wptr_old = ring->wptr; in amdgpu_ring_alloc()
162 count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); in amdgpu_ring_commit()
193 ring->wptr = ring->wptr_old; in amdgpu_ring_undo()
238 size = ring->wptr + (ring->ring_size / 4); in amdgpu_ring_backup()
476 uint32_t rptr, wptr, rptr_next; in amdgpu_debugfs_ring_info() local
482 wptr = amdgpu_ring_get_wptr(ring); in amdgpu_debugfs_ring_info()
484 wptr, wptr); in amdgpu_debugfs_ring_info()
493 ring->wptr, ring->wptr); in amdgpu_debugfs_ring_info()
Dtonga_ih.c199 u32 wptr, tmp; in tonga_ih_get_wptr() local
202 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
204 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
206 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in tonga_ih_get_wptr()
207 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
213 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in tonga_ih_get_wptr()
214 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in tonga_ih_get_wptr()
219 return (wptr & adev->irq.ih.ptr_mask); in tonga_ih_get_wptr()
Dcz_ih.c191 u32 wptr, tmp; in cz_ih_get_wptr() local
193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cz_ih_get_wptr()
195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in cz_ih_get_wptr()
196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cz_ih_get_wptr()
208 return (wptr & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
Diceland_ih.c191 u32 wptr, tmp; in iceland_ih_get_wptr() local
193 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in iceland_ih_get_wptr()
195 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { in iceland_ih_get_wptr()
196 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
202 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
203 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in iceland_ih_get_wptr()
208 return (wptr & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
Dcik_ih.c189 u32 wptr, tmp; in cik_ih_get_wptr() local
191 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cik_ih_get_wptr()
193 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
194 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
200 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
201 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cik_ih_get_wptr()
206 return (wptr & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
Damdgpu_ih.c179 u32 wptr; in amdgpu_ih_process() local
184 wptr = amdgpu_ih_get_wptr(adev); in amdgpu_ih_process()
191 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr); in amdgpu_ih_process()
196 while (adev->irq.ih.rptr != wptr) { in amdgpu_ih_process()
214 wptr = amdgpu_ih_get_wptr(adev); in amdgpu_ih_process()
215 if (wptr != adev->irq.ih.rptr) in amdgpu_ih_process()
Dvce_v2_0.c94 WREG32(mmVCE_RB_WPTR, ring->wptr); in vce_v2_0_ring_set_wptr()
96 WREG32(mmVCE_RB_WPTR2, ring->wptr); in vce_v2_0_ring_set_wptr()
117 WREG32(mmVCE_RB_RPTR, ring->wptr); in vce_v2_0_start()
118 WREG32(mmVCE_RB_WPTR, ring->wptr); in vce_v2_0_start()
124 WREG32(mmVCE_RB_RPTR2, ring->wptr); in vce_v2_0_start()
125 WREG32(mmVCE_RB_WPTR2, ring->wptr); in vce_v2_0_start()
Dvce_v3_0.c101 WREG32(mmVCE_RB_WPTR, ring->wptr); in vce_v3_0_ring_set_wptr()
103 WREG32(mmVCE_RB_WPTR2, ring->wptr); in vce_v3_0_ring_set_wptr()
188 WREG32(mmVCE_RB_RPTR, ring->wptr); in vce_v3_0_start()
189 WREG32(mmVCE_RB_WPTR, ring->wptr); in vce_v3_0_start()
195 WREG32(mmVCE_RB_RPTR2, ring->wptr); in vce_v3_0_start()
196 WREG32(mmVCE_RB_WPTR2, ring->wptr); in vce_v3_0_start()
/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c112 adreno_gpu->memptrs->wptr = 0; in adreno_recover()
207 uint32_t wptr; in adreno_flush() local
214 wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1); in adreno_flush()
219 adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); in adreno_flush()
225 uint32_t wptr = get_wptr(gpu->rb); in adreno_idle() local
228 if (spin_until(adreno_gpu->memptrs->rptr == wptr)) in adreno_idle()
248 seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); in adreno_show()
289 printk("wptr: %d\n", adreno_gpu->memptrs->wptr); in adreno_dump_info()
322 uint32_t wptr = get_wptr(gpu->rb); in ring_freewords() local
324 return (rptr + (size - 1) - wptr) % size; in ring_freewords()
/drivers/infiniband/hw/cxgb3/
Dcxio_hal.c609 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, in cxio_hal_ctrl_qp_write_mem()
613 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
617 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); in cxio_hal_ctrl_qp_write_mem()
620 rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
629 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
671 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % in cxio_hal_ctrl_qp_write_mem()
675 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; in cxio_hal_ctrl_qp_write_mem()
682 Q_GENBIT(rdev_p->ctrl_qp.wptr, in cxio_hal_ctrl_qp_write_mem()
688 rdev_p->ctrl_qp.wptr++; in cxio_hal_ctrl_qp_write_mem()
706 u32 wptr; in __cxio_tpt_op() local
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Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) argument
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ argument
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) argument
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) argument
697 u32 wptr; /* idx to next available WR slot */ member
718 u32 wptr; member
/drivers/video/fbdev/
Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()
/drivers/staging/media/lirc/
Dlirc_parallel.c85 static unsigned int wptr; variable
210 nwptr = (wptr + 1) & (RBUF_SIZE - 1); in rbuf_write()
217 rbuf[wptr] = signal; in rbuf_write()
218 wptr = nwptr; in rbuf_write()
338 if (rptr != wptr) { in lirc_read()
457 if (rptr != wptr) in lirc_poll()
524 wptr = 0; in lirc_open()
/drivers/tty/serial/
Dmen_z135_uart.c301 u32 wptr; in men_z135_handle_tx() local
323 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_handle_tx()
324 txc = (wptr >> 16) & 0x3ff; in men_z135_handle_tx()
325 wptr &= 0x3ff; in men_z135_handle_tx()
341 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) in men_z135_handle_tx()
342 n = 4 - BYTES_TO_ALIGN(wptr); in men_z135_handle_tx()
463 u32 wptr; in men_z135_tx_empty() local
466 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); in men_z135_tx_empty()
467 txc = (wptr >> 16) & 0x3ff; in men_z135_tx_empty()
/drivers/scsi/qla2xxx/
Dqla_sup.c550 uint16_t cnt, chksum, *wptr; in qla2xxx_find_flt_start() local
611 wptr = (uint16_t *)req->ring; in qla2xxx_find_flt_start()
614 chksum += le16_to_cpu(*wptr++); in qla2xxx_find_flt_start()
668 uint16_t *wptr; in qla2xxx_get_flt_info() local
689 wptr = (uint16_t *)req->ring; in qla2xxx_get_flt_info()
694 if (*wptr == cpu_to_le16(0xffff)) in qla2xxx_get_flt_info()
706 chksum += le16_to_cpu(*wptr++); in qla2xxx_get_flt_info()
884 uint16_t *wptr; in qla2xxx_get_fdt_info() local
891 wptr = (uint16_t *)req->ring; in qla2xxx_get_fdt_info()
895 if (*wptr == cpu_to_le16(0xffff)) in qla2xxx_get_fdt_info()
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