1 /*
2 * linux/include/linux/clk-provider.h
3 *
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
13
14 #include <linux/io.h>
15 #include <linux/of.h>
16
17 #ifdef CONFIG_COMMON_CLK
18
19 /*
20 * flags used across common struct clk. these flags should only affect the
21 * top-level framework. custom flags for dealing with hardware specifics
22 * belong in struct clk_foo
23 */
24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
28 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
32 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
33 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
34
35 struct clk;
36 struct clk_hw;
37 struct clk_core;
38 struct dentry;
39
40 /**
41 * struct clk_rate_request - Structure encoding the clk constraints that
42 * a clock user might require.
43 *
44 * @rate: Requested clock rate. This field will be adjusted by
45 * clock drivers according to hardware capabilities.
46 * @min_rate: Minimum rate imposed by clk users.
47 * @max_rate: Maximum rate a imposed by clk users.
48 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
49 * requested constraints.
50 * @best_parent_hw: The most appropriate parent clock that fulfills the
51 * requested constraints.
52 *
53 */
54 struct clk_rate_request {
55 unsigned long rate;
56 unsigned long min_rate;
57 unsigned long max_rate;
58 unsigned long best_parent_rate;
59 struct clk_hw *best_parent_hw;
60 };
61
62 /**
63 * struct clk_ops - Callback operations for hardware clocks; these are to
64 * be provided by the clock implementation, and will be called by drivers
65 * through the clk_* api.
66 *
67 * @prepare: Prepare the clock for enabling. This must not return until
68 * the clock is fully prepared, and it's safe to call clk_enable.
69 * This callback is intended to allow clock implementations to
70 * do any initialisation that may sleep. Called with
71 * prepare_lock held.
72 *
73 * @unprepare: Release the clock from its prepared state. This will typically
74 * undo any work done in the @prepare callback. Called with
75 * prepare_lock held.
76 *
77 * @is_prepared: Queries the hardware to determine if the clock is prepared.
78 * This function is allowed to sleep. Optional, if this op is not
79 * set then the prepare count will be used.
80 *
81 * @unprepare_unused: Unprepare the clock atomically. Only called from
82 * clk_disable_unused for prepare clocks with special needs.
83 * Called with prepare mutex held. This function may sleep.
84 *
85 * @enable: Enable the clock atomically. This must not return until the
86 * clock is generating a valid clock signal, usable by consumer
87 * devices. Called with enable_lock held. This function must not
88 * sleep.
89 *
90 * @disable: Disable the clock atomically. Called with enable_lock held.
91 * This function must not sleep.
92 *
93 * @is_enabled: Queries the hardware to determine if the clock is enabled.
94 * This function must not sleep. Optional, if this op is not
95 * set then the enable count will be used.
96 *
97 * @disable_unused: Disable the clock atomically. Only called from
98 * clk_disable_unused for gate clocks with special needs.
99 * Called with enable_lock held. This function must not
100 * sleep.
101 *
102 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
103 * parent rate is an input parameter. It is up to the caller to
104 * ensure that the prepare_mutex is held across this call.
105 * Returns the calculated rate. Optional, but recommended - if
106 * this op is not set then clock rate will be initialized to 0.
107 *
108 * @round_rate: Given a target rate as input, returns the closest rate actually
109 * supported by the clock. The parent rate is an input/output
110 * parameter.
111 *
112 * @determine_rate: Given a target rate as input, returns the closest rate
113 * actually supported by the clock, and optionally the parent clock
114 * that should be used to provide the clock rate.
115 *
116 * @set_parent: Change the input source of this clock; for clocks with multiple
117 * possible parents specify a new parent by passing in the index
118 * as a u8 corresponding to the parent in either the .parent_names
119 * or .parents arrays. This function in affect translates an
120 * array index into the value programmed into the hardware.
121 * Returns 0 on success, -EERROR otherwise.
122 *
123 * @get_parent: Queries the hardware to determine the parent of a clock. The
124 * return value is a u8 which specifies the index corresponding to
125 * the parent clock. This index can be applied to either the
126 * .parent_names or .parents arrays. In short, this function
127 * translates the parent value read from hardware into an array
128 * index. Currently only called when the clock is initialized by
129 * __clk_init. This callback is mandatory for clocks with
130 * multiple parents. It is optional (and unnecessary) for clocks
131 * with 0 or 1 parents.
132 *
133 * @set_rate: Change the rate of this clock. The requested rate is specified
134 * by the second argument, which should typically be the return
135 * of .round_rate call. The third argument gives the parent rate
136 * which is likely helpful for most .set_rate implementation.
137 * Returns 0 on success, -EERROR otherwise.
138 *
139 * @set_rate_and_parent: Change the rate and the parent of this clock. The
140 * requested rate is specified by the second argument, which
141 * should typically be the return of .round_rate call. The
142 * third argument gives the parent rate which is likely helpful
143 * for most .set_rate_and_parent implementation. The fourth
144 * argument gives the parent index. This callback is optional (and
145 * unnecessary) for clocks with 0 or 1 parents as well as
146 * for clocks that can tolerate switching the rate and the parent
147 * separately via calls to .set_parent and .set_rate.
148 * Returns 0 on success, -EERROR otherwise.
149 *
150 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
151 * is expressed in ppb (parts per billion). The parent accuracy is
152 * an input parameter.
153 * Returns the calculated accuracy. Optional - if this op is not
154 * set then clock accuracy will be initialized to parent accuracy
155 * or 0 (perfect clock) if clock has no parent.
156 *
157 * @get_phase: Queries the hardware to get the current phase of a clock.
158 * Returned values are 0-359 degrees on success, negative
159 * error codes on failure.
160 *
161 * @set_phase: Shift the phase this clock signal in degrees specified
162 * by the second argument. Valid values for degrees are
163 * 0-359. Return 0 on success, otherwise -EERROR.
164 *
165 * @init: Perform platform-specific initialization magic.
166 * This is not not used by any of the basic clock types.
167 * Please consider other ways of solving initialization problems
168 * before using this callback, as its use is discouraged.
169 *
170 * @debug_init: Set up type-specific debugfs entries for this clock. This
171 * is called once, after the debugfs directory entry for this
172 * clock has been created. The dentry pointer representing that
173 * directory is provided as an argument. Called with
174 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
175 *
176 *
177 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
178 * implementations to split any work between atomic (enable) and sleepable
179 * (prepare) contexts. If enabling a clock requires code that might sleep,
180 * this must be done in clk_prepare. Clock enable code that will never be
181 * called in a sleepable context may be implemented in clk_enable.
182 *
183 * Typically, drivers will call clk_prepare when a clock may be needed later
184 * (eg. when a device is opened), and clk_enable when the clock is actually
185 * required (eg. from an interrupt). Note that clk_prepare MUST have been
186 * called before clk_enable.
187 */
188 struct clk_ops {
189 int (*prepare)(struct clk_hw *hw);
190 void (*unprepare)(struct clk_hw *hw);
191 int (*is_prepared)(struct clk_hw *hw);
192 void (*unprepare_unused)(struct clk_hw *hw);
193 int (*enable)(struct clk_hw *hw);
194 void (*disable)(struct clk_hw *hw);
195 int (*is_enabled)(struct clk_hw *hw);
196 void (*disable_unused)(struct clk_hw *hw);
197 unsigned long (*recalc_rate)(struct clk_hw *hw,
198 unsigned long parent_rate);
199 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
200 unsigned long *parent_rate);
201 int (*determine_rate)(struct clk_hw *hw,
202 struct clk_rate_request *req);
203 int (*set_parent)(struct clk_hw *hw, u8 index);
204 u8 (*get_parent)(struct clk_hw *hw);
205 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
206 unsigned long parent_rate);
207 int (*set_rate_and_parent)(struct clk_hw *hw,
208 unsigned long rate,
209 unsigned long parent_rate, u8 index);
210 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
211 unsigned long parent_accuracy);
212 int (*get_phase)(struct clk_hw *hw);
213 int (*set_phase)(struct clk_hw *hw, int degrees);
214 void (*init)(struct clk_hw *hw);
215 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
216 };
217
218 /**
219 * struct clk_init_data - holds init data that's common to all clocks and is
220 * shared between the clock provider and the common clock framework.
221 *
222 * @name: clock name
223 * @ops: operations this clock supports
224 * @parent_names: array of string names for all possible parents
225 * @num_parents: number of possible parents
226 * @flags: framework-level hints and quirks
227 */
228 struct clk_init_data {
229 const char *name;
230 const struct clk_ops *ops;
231 const char * const *parent_names;
232 u8 num_parents;
233 unsigned long flags;
234 };
235
236 /**
237 * struct clk_hw - handle for traversing from a struct clk to its corresponding
238 * hardware-specific structure. struct clk_hw should be declared within struct
239 * clk_foo and then referenced by the struct clk instance that uses struct
240 * clk_foo's clk_ops
241 *
242 * @core: pointer to the struct clk_core instance that points back to this
243 * struct clk_hw instance
244 *
245 * @clk: pointer to the per-user struct clk instance that can be used to call
246 * into the clk API
247 *
248 * @init: pointer to struct clk_init_data that contains the init data shared
249 * with the common clock framework.
250 */
251 struct clk_hw {
252 struct clk_core *core;
253 struct clk *clk;
254 const struct clk_init_data *init;
255 };
256
257 /*
258 * DOC: Basic clock implementations common to many platforms
259 *
260 * Each basic clock hardware type is comprised of a structure describing the
261 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
262 * unique flags for that hardware type, a registration function and an
263 * alternative macro for static initialization
264 */
265
266 /**
267 * struct clk_fixed_rate - fixed-rate clock
268 * @hw: handle between common and hardware-specific interfaces
269 * @fixed_rate: constant frequency of clock
270 */
271 struct clk_fixed_rate {
272 struct clk_hw hw;
273 unsigned long fixed_rate;
274 unsigned long fixed_accuracy;
275 u8 flags;
276 };
277
278 extern const struct clk_ops clk_fixed_rate_ops;
279 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
280 const char *parent_name, unsigned long flags,
281 unsigned long fixed_rate);
282 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
283 const char *name, const char *parent_name, unsigned long flags,
284 unsigned long fixed_rate, unsigned long fixed_accuracy);
285
286 void of_fixed_clk_setup(struct device_node *np);
287
288 /**
289 * struct clk_gate - gating clock
290 *
291 * @hw: handle between common and hardware-specific interfaces
292 * @reg: register controlling gate
293 * @bit_idx: single bit controlling gate
294 * @flags: hardware-specific flags
295 * @lock: register lock
296 *
297 * Clock which can gate its output. Implements .enable & .disable
298 *
299 * Flags:
300 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
301 * enable the clock. Setting this flag does the opposite: setting the bit
302 * disable the clock and clearing it enables the clock
303 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
304 * of this register, and mask of gate bits are in higher 16-bit of this
305 * register. While setting the gate bits, higher 16-bit should also be
306 * updated to indicate changing gate bits.
307 */
308 struct clk_gate {
309 struct clk_hw hw;
310 void __iomem *reg;
311 u8 bit_idx;
312 u8 flags;
313 spinlock_t *lock;
314 };
315
316 #define CLK_GATE_SET_TO_DISABLE BIT(0)
317 #define CLK_GATE_HIWORD_MASK BIT(1)
318
319 extern const struct clk_ops clk_gate_ops;
320 struct clk *clk_register_gate(struct device *dev, const char *name,
321 const char *parent_name, unsigned long flags,
322 void __iomem *reg, u8 bit_idx,
323 u8 clk_gate_flags, spinlock_t *lock);
324 void clk_unregister_gate(struct clk *clk);
325
326 struct clk_div_table {
327 unsigned int val;
328 unsigned int div;
329 };
330
331 /**
332 * struct clk_divider - adjustable divider clock
333 *
334 * @hw: handle between common and hardware-specific interfaces
335 * @reg: register containing the divider
336 * @shift: shift to the divider bit field
337 * @width: width of the divider bit field
338 * @table: array of value/divider pairs, last entry should have div = 0
339 * @lock: register lock
340 *
341 * Clock with an adjustable divider affecting its output frequency. Implements
342 * .recalc_rate, .set_rate and .round_rate
343 *
344 * Flags:
345 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
346 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
347 * the raw value read from the register, with the value of zero considered
348 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
349 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
350 * the hardware register
351 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
352 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
353 * Some hardware implementations gracefully handle this case and allow a
354 * zero divisor by not modifying their input clock
355 * (divide by one / bypass).
356 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
357 * of this register, and mask of divider bits are in higher 16-bit of this
358 * register. While setting the divider bits, higher 16-bit should also be
359 * updated to indicate changing divider bits.
360 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
361 * to the closest integer instead of the up one.
362 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
363 * not be changed by the clock framework.
364 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
365 * except when the value read from the register is zero, the divisor is
366 * 2^width of the field.
367 */
368 struct clk_divider {
369 struct clk_hw hw;
370 void __iomem *reg;
371 u8 shift;
372 u8 width;
373 u8 flags;
374 const struct clk_div_table *table;
375 spinlock_t *lock;
376 };
377
378 #define CLK_DIVIDER_ONE_BASED BIT(0)
379 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
380 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
381 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
382 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
383 #define CLK_DIVIDER_READ_ONLY BIT(5)
384 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
385
386 extern const struct clk_ops clk_divider_ops;
387 extern const struct clk_ops clk_divider_ro_ops;
388
389 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
390 unsigned int val, const struct clk_div_table *table,
391 unsigned long flags);
392 long divider_round_rate(struct clk_hw *hw, unsigned long rate,
393 unsigned long *prate, const struct clk_div_table *table,
394 u8 width, unsigned long flags);
395 int divider_get_val(unsigned long rate, unsigned long parent_rate,
396 const struct clk_div_table *table, u8 width,
397 unsigned long flags);
398
399 struct clk *clk_register_divider(struct device *dev, const char *name,
400 const char *parent_name, unsigned long flags,
401 void __iomem *reg, u8 shift, u8 width,
402 u8 clk_divider_flags, spinlock_t *lock);
403 struct clk *clk_register_divider_table(struct device *dev, const char *name,
404 const char *parent_name, unsigned long flags,
405 void __iomem *reg, u8 shift, u8 width,
406 u8 clk_divider_flags, const struct clk_div_table *table,
407 spinlock_t *lock);
408 void clk_unregister_divider(struct clk *clk);
409
410 /**
411 * struct clk_mux - multiplexer clock
412 *
413 * @hw: handle between common and hardware-specific interfaces
414 * @reg: register controlling multiplexer
415 * @shift: shift to multiplexer bit field
416 * @width: width of mutliplexer bit field
417 * @flags: hardware-specific flags
418 * @lock: register lock
419 *
420 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
421 * and .recalc_rate
422 *
423 * Flags:
424 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
425 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
426 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
427 * register, and mask of mux bits are in higher 16-bit of this register.
428 * While setting the mux bits, higher 16-bit should also be updated to
429 * indicate changing mux bits.
430 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
431 * frequency.
432 */
433 struct clk_mux {
434 struct clk_hw hw;
435 void __iomem *reg;
436 u32 *table;
437 u32 mask;
438 u8 shift;
439 u8 flags;
440 spinlock_t *lock;
441 };
442
443 #define CLK_MUX_INDEX_ONE BIT(0)
444 #define CLK_MUX_INDEX_BIT BIT(1)
445 #define CLK_MUX_HIWORD_MASK BIT(2)
446 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
447 #define CLK_MUX_ROUND_CLOSEST BIT(4)
448
449 extern const struct clk_ops clk_mux_ops;
450 extern const struct clk_ops clk_mux_ro_ops;
451
452 struct clk *clk_register_mux(struct device *dev, const char *name,
453 const char * const *parent_names, u8 num_parents,
454 unsigned long flags,
455 void __iomem *reg, u8 shift, u8 width,
456 u8 clk_mux_flags, spinlock_t *lock);
457
458 struct clk *clk_register_mux_table(struct device *dev, const char *name,
459 const char * const *parent_names, u8 num_parents,
460 unsigned long flags,
461 void __iomem *reg, u8 shift, u32 mask,
462 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
463
464 void clk_unregister_mux(struct clk *clk);
465
466 void of_fixed_factor_clk_setup(struct device_node *node);
467
468 /**
469 * struct clk_fixed_factor - fixed multiplier and divider clock
470 *
471 * @hw: handle between common and hardware-specific interfaces
472 * @mult: multiplier
473 * @div: divider
474 *
475 * Clock with a fixed multiplier and divider. The output frequency is the
476 * parent clock rate divided by div and multiplied by mult.
477 * Implements .recalc_rate, .set_rate and .round_rate
478 */
479
480 struct clk_fixed_factor {
481 struct clk_hw hw;
482 unsigned int mult;
483 unsigned int div;
484 };
485
486 extern const struct clk_ops clk_fixed_factor_ops;
487 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
488 const char *parent_name, unsigned long flags,
489 unsigned int mult, unsigned int div);
490
491 /**
492 * struct clk_fractional_divider - adjustable fractional divider clock
493 *
494 * @hw: handle between common and hardware-specific interfaces
495 * @reg: register containing the divider
496 * @mshift: shift to the numerator bit field
497 * @mwidth: width of the numerator bit field
498 * @nshift: shift to the denominator bit field
499 * @nwidth: width of the denominator bit field
500 * @lock: register lock
501 *
502 * Clock with adjustable fractional divider affecting its output frequency.
503 */
504 struct clk_fractional_divider {
505 struct clk_hw hw;
506 void __iomem *reg;
507 u8 mshift;
508 u8 mwidth;
509 u32 mmask;
510 u8 nshift;
511 u8 nwidth;
512 u32 nmask;
513 u8 flags;
514 spinlock_t *lock;
515 };
516
517 extern const struct clk_ops clk_fractional_divider_ops;
518 struct clk *clk_register_fractional_divider(struct device *dev,
519 const char *name, const char *parent_name, unsigned long flags,
520 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
521 u8 clk_divider_flags, spinlock_t *lock);
522
523 /**
524 * struct clk_multiplier - adjustable multiplier clock
525 *
526 * @hw: handle between common and hardware-specific interfaces
527 * @reg: register containing the multiplier
528 * @shift: shift to the multiplier bit field
529 * @width: width of the multiplier bit field
530 * @lock: register lock
531 *
532 * Clock with an adjustable multiplier affecting its output frequency.
533 * Implements .recalc_rate, .set_rate and .round_rate
534 *
535 * Flags:
536 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
537 * from the register, with 0 being a valid value effectively
538 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
539 * set, then a null multiplier will be considered as a bypass,
540 * leaving the parent rate unmodified.
541 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
542 * rounded to the closest integer instead of the down one.
543 */
544 struct clk_multiplier {
545 struct clk_hw hw;
546 void __iomem *reg;
547 u8 shift;
548 u8 width;
549 u8 flags;
550 spinlock_t *lock;
551 };
552
553 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
554 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
555
556 extern const struct clk_ops clk_multiplier_ops;
557
558 /***
559 * struct clk_composite - aggregate clock of mux, divider and gate clocks
560 *
561 * @hw: handle between common and hardware-specific interfaces
562 * @mux_hw: handle between composite and hardware-specific mux clock
563 * @rate_hw: handle between composite and hardware-specific rate clock
564 * @gate_hw: handle between composite and hardware-specific gate clock
565 * @mux_ops: clock ops for mux
566 * @rate_ops: clock ops for rate
567 * @gate_ops: clock ops for gate
568 */
569 struct clk_composite {
570 struct clk_hw hw;
571 struct clk_ops ops;
572
573 struct clk_hw *mux_hw;
574 struct clk_hw *rate_hw;
575 struct clk_hw *gate_hw;
576
577 const struct clk_ops *mux_ops;
578 const struct clk_ops *rate_ops;
579 const struct clk_ops *gate_ops;
580 };
581
582 struct clk *clk_register_composite(struct device *dev, const char *name,
583 const char * const *parent_names, int num_parents,
584 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
585 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
586 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
587 unsigned long flags);
588
589 /***
590 * struct clk_gpio_gate - gpio gated clock
591 *
592 * @hw: handle between common and hardware-specific interfaces
593 * @gpiod: gpio descriptor
594 *
595 * Clock with a gpio control for enabling and disabling the parent clock.
596 * Implements .enable, .disable and .is_enabled
597 */
598
599 struct clk_gpio {
600 struct clk_hw hw;
601 struct gpio_desc *gpiod;
602 };
603
604 extern const struct clk_ops clk_gpio_gate_ops;
605 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
606 const char *parent_name, unsigned gpio, bool active_low,
607 unsigned long flags);
608
609 void of_gpio_clk_gate_setup(struct device_node *node);
610
611 /**
612 * struct clk_gpio_mux - gpio controlled clock multiplexer
613 *
614 * @hw: see struct clk_gpio
615 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
616 *
617 * Clock with a gpio control for selecting the parent clock.
618 * Implements .get_parent, .set_parent and .determine_rate
619 */
620
621 extern const struct clk_ops clk_gpio_mux_ops;
622 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
623 const char * const *parent_names, u8 num_parents, unsigned gpio,
624 bool active_low, unsigned long flags);
625
626 void of_gpio_mux_clk_setup(struct device_node *node);
627
628 /**
629 * clk_register - allocate a new clock, register it and return an opaque cookie
630 * @dev: device that is registering this clock
631 * @hw: link to hardware-specific clock data
632 *
633 * clk_register is the primary interface for populating the clock tree with new
634 * clock nodes. It returns a pointer to the newly allocated struct clk which
635 * cannot be dereferenced by driver code but may be used in conjuction with the
636 * rest of the clock API. In the event of an error clk_register will return an
637 * error code; drivers must test for an error code after calling clk_register.
638 */
639 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
640 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
641
642 void clk_unregister(struct clk *clk);
643 void devm_clk_unregister(struct device *dev, struct clk *clk);
644
645 /* helper functions */
646 const char *__clk_get_name(const struct clk *clk);
647 const char *clk_hw_get_name(const struct clk_hw *hw);
648 struct clk_hw *__clk_get_hw(struct clk *clk);
649 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
650 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
651 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
652 unsigned int index);
653 unsigned int __clk_get_enable_count(struct clk *clk);
654 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
655 unsigned long __clk_get_flags(struct clk *clk);
656 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
657 bool clk_hw_is_prepared(const struct clk_hw *hw);
658 bool clk_hw_is_enabled(const struct clk_hw *hw);
659 bool __clk_is_enabled(struct clk *clk);
660 struct clk *__clk_lookup(const char *name);
661 int __clk_mux_determine_rate(struct clk_hw *hw,
662 struct clk_rate_request *req);
663 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
664 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
665 struct clk_rate_request *req);
666 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
667 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
668 unsigned long max_rate);
669
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)670 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
671 {
672 dst->clk = src->clk;
673 dst->core = src->core;
674 }
675
676 /*
677 * FIXME clock api without lock protection
678 */
679 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
680
681 struct of_device_id;
682
683 typedef void (*of_clk_init_cb_t)(struct device_node *);
684
685 struct clk_onecell_data {
686 struct clk **clks;
687 unsigned int clk_num;
688 };
689
690 extern struct of_device_id __clk_of_table;
691
692 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
693
694 #ifdef CONFIG_OF
695 int of_clk_add_provider(struct device_node *np,
696 struct clk *(*clk_src_get)(struct of_phandle_args *args,
697 void *data),
698 void *data);
699 void of_clk_del_provider(struct device_node *np);
700 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
701 void *data);
702 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
703 int of_clk_get_parent_count(struct device_node *np);
704 int of_clk_parent_fill(struct device_node *np, const char **parents,
705 unsigned int size);
706 const char *of_clk_get_parent_name(struct device_node *np, int index);
707
708 void of_clk_init(const struct of_device_id *matches);
709
710 #else /* !CONFIG_OF */
711
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)712 static inline int of_clk_add_provider(struct device_node *np,
713 struct clk *(*clk_src_get)(struct of_phandle_args *args,
714 void *data),
715 void *data)
716 {
717 return 0;
718 }
719 #define of_clk_del_provider(np) \
720 { while (0); }
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)721 static inline struct clk *of_clk_src_simple_get(
722 struct of_phandle_args *clkspec, void *data)
723 {
724 return ERR_PTR(-ENOENT);
725 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)726 static inline struct clk *of_clk_src_onecell_get(
727 struct of_phandle_args *clkspec, void *data)
728 {
729 return ERR_PTR(-ENOENT);
730 }
of_clk_get_parent_count(struct device_node * np)731 static inline int of_clk_get_parent_count(struct device_node *np)
732 {
733 return 0;
734 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)735 static inline int of_clk_parent_fill(struct device_node *np,
736 const char **parents, unsigned int size)
737 {
738 return 0;
739 }
of_clk_get_parent_name(struct device_node * np,int index)740 static inline const char *of_clk_get_parent_name(struct device_node *np,
741 int index)
742 {
743 return NULL;
744 }
745 #define of_clk_init(matches) \
746 { while (0); }
747 #endif /* CONFIG_OF */
748
749 /*
750 * wrap access to peripherals in accessor routines
751 * for improved portability across platforms
752 */
753
754 #if IS_ENABLED(CONFIG_PPC)
755
clk_readl(u32 __iomem * reg)756 static inline u32 clk_readl(u32 __iomem *reg)
757 {
758 return ioread32be(reg);
759 }
760
clk_writel(u32 val,u32 __iomem * reg)761 static inline void clk_writel(u32 val, u32 __iomem *reg)
762 {
763 iowrite32be(val, reg);
764 }
765
766 #else /* platform dependent I/O accessors */
767
clk_readl(u32 __iomem * reg)768 static inline u32 clk_readl(u32 __iomem *reg)
769 {
770 return readl(reg);
771 }
772
clk_writel(u32 val,u32 __iomem * reg)773 static inline void clk_writel(u32 val, u32 __iomem *reg)
774 {
775 writel(val, reg);
776 }
777
778 #endif /* platform dependent I/O accessors */
779
780 #ifdef CONFIG_DEBUG_FS
781 struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
782 void *data, const struct file_operations *fops);
783 #endif
784
785 #endif /* CONFIG_COMMON_CLK */
786 #endif /* CLK_PROVIDER_H */
787