1 /*
2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19 #ifndef __ASM_ARM_KVM_VGIC_H
20 #define __ASM_ARM_KVM_VGIC_H
21
22 #include <linux/kernel.h>
23 #include <linux/kvm.h>
24 #include <linux/irqreturn.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
27 #include <kvm/iodev.h>
28
29 #define VGIC_NR_IRQS_LEGACY 256
30 #define VGIC_NR_SGIS 16
31 #define VGIC_NR_PPIS 16
32 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33
34 #define VGIC_V2_MAX_LRS (1 << 6)
35 #define VGIC_V3_MAX_LRS 16
36 #define VGIC_MAX_IRQS 1024
37 #define VGIC_V2_MAX_CPUS 8
38 #define VGIC_V3_MAX_CPUS 255
39
40 #if (VGIC_NR_IRQS_LEGACY & 31)
41 #error "VGIC_NR_IRQS must be a multiple of 32"
42 #endif
43
44 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
45 #error "VGIC_NR_IRQS must be <= 1024"
46 #endif
47
48 /*
49 * The GIC distributor registers describing interrupts have two parts:
50 * - 32 per-CPU interrupts (SGI + PPI)
51 * - a bunch of shared interrupts (SPI)
52 */
53 struct vgic_bitmap {
54 /*
55 * - One UL per VCPU for private interrupts (assumes UL is at
56 * least 32 bits)
57 * - As many UL as necessary for shared interrupts.
58 *
59 * The private interrupts are accessed via the "private"
60 * field, one UL per vcpu (the state for vcpu n is in
61 * private[n]). The shared interrupts are accessed via the
62 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
63 */
64 unsigned long *private;
65 unsigned long *shared;
66 };
67
68 struct vgic_bytemap {
69 /*
70 * - 8 u32 per VCPU for private interrupts
71 * - As many u32 as necessary for shared interrupts.
72 *
73 * The private interrupts are accessed via the "private"
74 * field, (the state for vcpu n is in private[n*8] to
75 * private[n*8 + 7]). The shared interrupts are accessed via
76 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
77 * shared[(n-32)/4] word).
78 */
79 u32 *private;
80 u32 *shared;
81 };
82
83 struct kvm_vcpu;
84
85 enum vgic_type {
86 VGIC_V2, /* Good ol' GICv2 */
87 VGIC_V3, /* New fancy GICv3 */
88 };
89
90 #define LR_STATE_PENDING (1 << 0)
91 #define LR_STATE_ACTIVE (1 << 1)
92 #define LR_STATE_MASK (3 << 0)
93 #define LR_EOI_INT (1 << 2)
94 #define LR_HW (1 << 3)
95
96 struct vgic_lr {
97 unsigned irq:10;
98 union {
99 unsigned hwirq:10;
100 unsigned source:3;
101 };
102 unsigned state:4;
103 };
104
105 struct vgic_vmcr {
106 u32 ctlr;
107 u32 abpr;
108 u32 bpr;
109 u32 pmr;
110 };
111
112 struct vgic_ops {
113 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
114 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
115 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
116 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
117 void (*clear_eisr)(struct kvm_vcpu *vcpu);
118 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
119 void (*enable_underflow)(struct kvm_vcpu *vcpu);
120 void (*disable_underflow)(struct kvm_vcpu *vcpu);
121 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
122 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
123 void (*enable)(struct kvm_vcpu *vcpu);
124 };
125
126 struct vgic_params {
127 /* vgic type */
128 enum vgic_type type;
129 /* Physical address of vgic virtual cpu interface */
130 phys_addr_t vcpu_base;
131 /* Number of list registers */
132 u32 nr_lr;
133 /* Interrupt number */
134 unsigned int maint_irq;
135 /* Virtual control interface base address */
136 void __iomem *vctrl_base;
137 int max_gic_vcpus;
138 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
139 bool can_emulate_gicv2;
140 };
141
142 struct vgic_vm_ops {
143 bool (*queue_sgi)(struct kvm_vcpu *, int irq);
144 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
145 int (*init_model)(struct kvm *);
146 int (*map_resources)(struct kvm *, const struct vgic_params *);
147 };
148
149 struct vgic_io_device {
150 gpa_t addr;
151 int len;
152 const struct vgic_io_range *reg_ranges;
153 struct kvm_vcpu *redist_vcpu;
154 struct kvm_io_device dev;
155 };
156
157 struct irq_phys_map {
158 u32 virt_irq;
159 u32 phys_irq;
160 u32 irq;
161 };
162
163 struct irq_phys_map_entry {
164 struct list_head entry;
165 struct rcu_head rcu;
166 struct irq_phys_map map;
167 };
168
169 struct vgic_dist {
170 spinlock_t lock;
171 bool in_kernel;
172 bool ready;
173
174 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
175 u32 vgic_model;
176
177 int nr_cpus;
178 int nr_irqs;
179
180 /* Virtual control interface mapping */
181 void __iomem *vctrl_base;
182
183 /* Distributor and vcpu interface mapping in the guest */
184 phys_addr_t vgic_dist_base;
185 /* GICv2 and GICv3 use different mapped register blocks */
186 union {
187 phys_addr_t vgic_cpu_base;
188 phys_addr_t vgic_redist_base;
189 };
190
191 /* Distributor enabled */
192 u32 enabled;
193
194 /* Interrupt enabled (one bit per IRQ) */
195 struct vgic_bitmap irq_enabled;
196
197 /* Level-triggered interrupt external input is asserted */
198 struct vgic_bitmap irq_level;
199
200 /*
201 * Interrupt state is pending on the distributor
202 */
203 struct vgic_bitmap irq_pending;
204
205 /*
206 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
207 * interrupts. Essentially holds the state of the flip-flop in
208 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
209 * Once set, it is only cleared for level-triggered interrupts on
210 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
211 */
212 struct vgic_bitmap irq_soft_pend;
213
214 /* Level-triggered interrupt queued on VCPU interface */
215 struct vgic_bitmap irq_queued;
216
217 /* Interrupt was active when unqueue from VCPU interface */
218 struct vgic_bitmap irq_active;
219
220 /* Interrupt priority. Not used yet. */
221 struct vgic_bytemap irq_priority;
222
223 /* Level/edge triggered */
224 struct vgic_bitmap irq_cfg;
225
226 /*
227 * Source CPU per SGI and target CPU:
228 *
229 * Each byte represent a SGI observable on a VCPU, each bit of
230 * this byte indicating if the corresponding VCPU has
231 * generated this interrupt. This is a GICv2 feature only.
232 *
233 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
234 * the SGIs observable on VCPUn.
235 */
236 u8 *irq_sgi_sources;
237
238 /*
239 * Target CPU for each SPI:
240 *
241 * Array of available SPI, each byte indicating the target
242 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
243 */
244 u8 *irq_spi_cpu;
245
246 /*
247 * Reverse lookup of irq_spi_cpu for faster compute pending:
248 *
249 * Array of bitmaps, one per VCPU, describing if IRQn is
250 * routed to a particular VCPU.
251 */
252 struct vgic_bitmap *irq_spi_target;
253
254 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
255 u32 *irq_spi_mpidr;
256
257 /* Bitmap indicating which CPU has something pending */
258 unsigned long *irq_pending_on_cpu;
259
260 /* Bitmap indicating which CPU has active IRQs */
261 unsigned long *irq_active_on_cpu;
262
263 struct vgic_vm_ops vm_ops;
264 struct vgic_io_device dist_iodev;
265 struct vgic_io_device *redist_iodevs;
266
267 /* Virtual irq to hwirq mapping */
268 spinlock_t irq_phys_map_lock;
269 struct list_head irq_phys_map_list;
270 };
271
272 struct vgic_v2_cpu_if {
273 u32 vgic_hcr;
274 u32 vgic_vmcr;
275 u32 vgic_misr; /* Saved only */
276 u64 vgic_eisr; /* Saved only */
277 u64 vgic_elrsr; /* Saved only */
278 u32 vgic_apr;
279 u32 vgic_lr[VGIC_V2_MAX_LRS];
280 };
281
282 struct vgic_v3_cpu_if {
283 #ifdef CONFIG_KVM_ARM_VGIC_V3
284 u32 vgic_hcr;
285 u32 vgic_vmcr;
286 u32 vgic_sre; /* Restored only, change ignored */
287 u32 vgic_misr; /* Saved only */
288 u32 vgic_eisr; /* Saved only */
289 u32 vgic_elrsr; /* Saved only */
290 u32 vgic_ap0r[4];
291 u32 vgic_ap1r[4];
292 u64 vgic_lr[VGIC_V3_MAX_LRS];
293 #endif
294 };
295
296 struct vgic_cpu {
297 /* Pending/active/both interrupts on this VCPU */
298 DECLARE_BITMAP(pending_percpu, VGIC_NR_PRIVATE_IRQS);
299 DECLARE_BITMAP(active_percpu, VGIC_NR_PRIVATE_IRQS);
300 DECLARE_BITMAP(pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
301
302 /* Pending/active/both shared interrupts, dynamically sized */
303 unsigned long *pending_shared;
304 unsigned long *active_shared;
305 unsigned long *pend_act_shared;
306
307 /* Number of list registers on this CPU */
308 int nr_lr;
309
310 /* CPU vif control registers for world switch */
311 union {
312 struct vgic_v2_cpu_if vgic_v2;
313 struct vgic_v3_cpu_if vgic_v3;
314 };
315
316 /* Protected by the distributor's irq_phys_map_lock */
317 struct list_head irq_phys_map_list;
318 };
319
320 #define LR_EMPTY 0xff
321
322 #define INT_STATUS_EOI (1 << 0)
323 #define INT_STATUS_UNDERFLOW (1 << 1)
324
325 struct kvm;
326 struct kvm_vcpu;
327
328 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
329 int kvm_vgic_hyp_init(void);
330 int kvm_vgic_map_resources(struct kvm *kvm);
331 int kvm_vgic_get_max_vcpus(void);
332 void kvm_vgic_early_init(struct kvm *kvm);
333 int kvm_vgic_create(struct kvm *kvm, u32 type);
334 void kvm_vgic_destroy(struct kvm *kvm);
335 void kvm_vgic_vcpu_early_init(struct kvm_vcpu *vcpu);
336 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
337 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
338 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
339 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
340 bool level);
341 int kvm_vgic_inject_mapped_irq(struct kvm *kvm, int cpuid,
342 struct irq_phys_map *map, bool level);
343 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
344 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
345 struct irq_phys_map *kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu,
346 int virt_irq, int irq);
347 int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
348 bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, struct irq_phys_map *map);
349
350 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
351 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
352 #define vgic_ready(k) ((k)->arch.vgic.ready)
353
354 int vgic_v2_probe(struct device_node *vgic_node,
355 const struct vgic_ops **ops,
356 const struct vgic_params **params);
357 #ifdef CONFIG_KVM_ARM_VGIC_V3
358 int vgic_v3_probe(struct device_node *vgic_node,
359 const struct vgic_ops **ops,
360 const struct vgic_params **params);
361 #else
vgic_v3_probe(struct device_node * vgic_node,const struct vgic_ops ** ops,const struct vgic_params ** params)362 static inline int vgic_v3_probe(struct device_node *vgic_node,
363 const struct vgic_ops **ops,
364 const struct vgic_params **params)
365 {
366 return -ENODEV;
367 }
368 #endif
369
370 #endif
371