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Searched refs:control_reg (Results 1 – 10 of 10) sorted by relevance

/sound/pci/echoaudio/
Dechoaudio_3g.c143 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
145 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; in set_spdif_bits()
149 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
153 control_reg |= E3G_SPDIF_SAMPLE_RATE0; in set_spdif_bits()
156 control_reg |= E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
161 control_reg |= E3G_SPDIF_PRO_MODE; in set_spdif_bits()
164 control_reg |= E3G_SPDIF_NOT_AUDIO; in set_spdif_bits()
166 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | in set_spdif_bits()
169 return control_reg; in set_spdif_bits()
177 u32 control_reg; in set_professional_spdif() local
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Dgina24_dsp.c124 u32 control_reg; in load_asic() local
154 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
155 err = write_control_reg(chip, control_reg, true); in load_asic()
164 u32 control_reg, clock; in set_sample_rate() local
182 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
183 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
198 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
223 control_reg |= clock; in set_sample_rate()
229 return write_control_reg(chip, control_reg, false); in set_sample_rate()
236 u32 control_reg, clocks_from_dsp; in set_input_clock() local
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Dmona_dsp.c117 u32 control_reg; in load_asic() local
150 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
151 err = write_control_reg(chip, control_reg, true); in load_asic()
198 u32 control_reg, clock; in set_sample_rate() local
244 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
245 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate()
246 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
261 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
286 control_reg |= clock; in set_sample_rate()
293 return write_control_reg(chip, control_reg, force_write); in set_sample_rate()
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Dlayla24_dsp.c159 u32 control_reg, clock, base_rate; in set_sample_rate() local
176 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
177 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
194 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
219 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
237 control_reg |= clock; in set_sample_rate()
242 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate()
244 return write_control_reg(chip, control_reg, false); in set_sample_rate()
251 u32 control_reg, clocks_from_dsp; in set_input_clock() local
254 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
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Dechoaudio_gml.c156 u32 control_reg; in set_professional_spdif() local
160 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
161 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif()
164 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif()
168 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif()
172 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
176 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif()
179 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
186 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
190 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
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Dindigo_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dindigodj_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dmia_dsp.c109 u32 control_reg; in set_sample_rate() local
113 control_reg = MIA_96000; in set_sample_rate()
116 control_reg = MIA_88200; in set_sample_rate()
119 control_reg = MIA_48000; in set_sample_rate()
122 control_reg = MIA_44100; in set_sample_rate()
125 control_reg = MIA_32000; in set_sample_rate()
135 control_reg |= MIA_SPDIF; in set_sample_rate()
138 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
143 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
63 if (control_reg != old_control_reg) { in set_sample_rate()
66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Decho3g_dsp.c120 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_phantom_power() local
123 control_reg |= E3G_PHANTOM_POWER; in set_phantom_power()
125 control_reg &= ~E3G_PHANTOM_POWER; in set_phantom_power()
128 return write_control_reg(chip, control_reg, in set_phantom_power()