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Searched refs:DIV4_NR (Results 1 – 12 of 12) sorted by relevance

/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c78 DIV4_NR }; enumerator
84 struct clk div4_clks[DIV4_NR] = {
147 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7269.c106 DIV4_NR }; enumerator
112 struct clk div4_clks[DIV4_NR] = {
178 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
/arch/sh/kernel/cpu/sh4a/
Dclock-sh7757.c63 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; enumerator
68 struct clk div4_clks[DIV4_NR] = {
Dclock-shx3.c62 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
67 struct clk div4_clks[DIV4_NR] = {
Dclock-sh7722.c123 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
125 struct clk div4_clks[DIV4_NR] = {
248 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7785.c67 DIV4_DU, DIV4_P, DIV4_NR }; enumerator
72 struct clk div4_clks[DIV4_NR] = {
Dclock-sh7366.c118 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator
123 struct clk div4_clks[DIV4_NR] = {
273 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7343.c115 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; enumerator
120 struct clk div4_clks[DIV4_NR] = {
280 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7723.c121 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
126 struct clk div4_clks[DIV4_NR] = {
296 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7786.c68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
73 struct clk div4_clks[DIV4_NR] = {
Dclock-sh7724.c160 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
165 struct clk div4_clks[DIV4_NR] = {
370 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); in arch_clk_init()
Dclock-sh7734.c70 enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR }; enumerator
75 struct clk div4_clks[DIV4_NR] = {