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/arch/alpha/lib/
Dev6-memcpy.S33 mov $16, $0 # E : copy dest to return
35 xor $16, $17, $1 # E : are source and dest alignments the same?
36 and $1, 7, $1 # E : are they the same mod 8?
40 and $16, 7, $1 # E : Are both 0mod8?
42 nop # E :
52 subq $18, 1, $18 # E : count--
53 addq $17, 1, $17 # E : src++
55 addq $16, 1, $16 # E : dest++
56 and $16, 7, $1 # E : Are we at 0mod8 yet?
61 cmple $18, 127, $1 # E : Can we unroll the loop?
[all …]
Dev6-memchr.S49 and $17, 0xff, $17 # E : L L U U : 00000000000000ch
52 cmpult $18, 9, $4 # E : small (< 1 quad) string?
53 or $2, $17, $17 # E : 000000000000chch
54 lda $3, -1($31) # E : U L L U
57 addq $16, $5, $5 # E : Max search address
58 or $2, $17, $17 # E : 00000000chchchch
61 or $2, $17, $17 # E : chchchchchchchch
67 mov $16, $0 # E :
68 nop # E :
69 or $7, $6, $1 # E : L U L U $1 = quadword starting at $16
[all …]
Dev6-memset.S52 and $17,255,$1 # E : 00000000000000ch
54 bis $16,$16,$0 # E : return value
57 addq $18,$16,$6 # E : max address to write to
58 bis $1,$2,$17 # E : 000000000000chch
62 or $3,$4,$3 # E : 00000000chch0000
64 xor $16,$6,$1 # E : will complete write be within one quadword?
67 or $17,$3,$17 # E : 00000000chchchch
68 or $2,$5,$2 # E : chchchch00000000
69 bic $1,7,$1 # E : fit within a single quadword?
70 and $16,7,$3 # E : Target addr misalignment
[all …]
Dev6-clear_user.S52 and $16, 7, $4 # .. E .. .. : find dest head misalignment
55 addq $0, $4, $1 # .. .. .. E : bias counter
56 and $1, 7, $2 # .. .. E .. : number of misaligned bytes in tail
59 srl $1, 3, $1 # .. E .. .. : number of quadwords to clear
69 addq $16, 8, $16 # E .. .. .. : L U U L
72 subq $1, 1, $1 # .. .. E .. :
73 addq $0, $4, $0 # .. E .. .. : bytes left -= 8 - misalignment
74 subq $0, 8, $0 # E .. .. .. : U L U L
85 subq $1, 16, $4 # .. .. .. E : If < 16, we can not use the huge loop
86 and $16, 0x3f, $2 # .. .. E .. : Forward work for huge loop
[all …]
Dev67-strncat.S37 lda $2, -1($31) # E :
40 andnot $16, 7, $16 # E :
41 nop # E :
42 or $2, $1, $1 # E :
44 nop # E :
45 nop # E :
46 cmpbge $31, $1, $2 # E : bits set iff byte == 0
50 addq $16, 8, $16 # E :
51 cmpbge $31, $1, $2 # E :
55 addq $16, $3, $16 # E :
[all …]
Dev6-divide.S108 subq $30,STACK,$30 # E :
113 bis $25,$25,divisor # E :
116 bis $24,$24,modulus # E :
118 bis $31,$31,quotient # E :
119 LONGIFY(divisor) # E : U L L U
122 LONGIFY(modulus) # E :
123 bis $31,1,mask # E :
143 1: cmpult divisor,modulus,compare # E :
144 s8addq divisor,$31,divisor # E :
145 s8addq mask,$31,mask # E :
[all …]
Dev6-csum_ipv6_magic.S68 and $16,7,$6 # E : src misalignment
78 cmoveq $6,$31,$22 # E : src aligned?
81 addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00
83 or $0,$22,$0 # E : 1st src word complete
85 or $18,$4,$18 # E : 000000CCDDAABBCC
88 and $17,7,$6 # E : dst misalignment
90 or $1,$5,$1 # E : 2nd src word complete
93 cmoveq $6,$31,$22 # E : dst aligned?
95 addq $20,$0,$20 # E : begin summing the words
99 or $2,$22,$2 # E : 1st dst word complete
[all …]
Dev6-copy_user.S49 subq $18, 32, $1 # .. E .. .. : Is this going to be a small copy?
52 and $16,7,$3 # .. .. .. E : is leading dest misalignment
55 subq $3, 8, $3 # E .. .. .. : L U U L : trip counter
63 addq $16,1,$16 # .. .. E .. : Section 3.8 in the CWG
64 addq $3,1,$3 # .. E .. .. :
65 nop # E .. .. .. : U L U L
72 addq $17,1,$17 # .. .. E .. : Section 3.8 in the CWG
73 subq $0,1,$0 # .. E .. .. :
81 and $17,7,$1 # .. .. .. E : Check _current_ source alignment
82 bic $0,7,$4 # .. .. E .. : number bytes as a quadword loop
[all …]
Dev67-strrchr.S34 and a1, 0xff, t2 # E : 00000000000000ch
39 mov zero, t6 # E : t6 is last match aligned addr
40 or t2, t4, a1 # E : 000000000000chch
42 mov zero, t8 # E : t8 is last match byte compare mask
44 andnot a0, 7, v0 # E : align source addr
45 or t5, t3, t3 # E : 00000000chch0000
49 or t4, a1, a1 # E : chch00000000chch
50 or t2, t3, t2 # E : 0000chchchch0000
51 or a1, t2, a1 # E : chchchchchchchch
52 lda t5, -1 # E : build garbage mask
[all …]
Dev6-stxcpy.S57 lda t2, -1 # E : build a mask against false zero
60 ornot t1, t2, t2 # E : (stall)
63 cmpbge zero, t2, t8 # E : bits set iff null found
64 or t0, t3, t1 # E : (stall)
74 addq a0, 8, a0 # E :
79 addq a1, 8, a1 # E :
80 cmpbge zero, t1, t8 # E : (3 cycle stall)
88 negq t8, t6 # E : find low bit set
89 and t8, t6, t12 # E : (stall)
92 and t12, 0x80, t6 # E : (stall)
[all …]
Dev67-strchr.S32 and a1, 0xff, t3 # E : 00000000000000ch
37 or t5, t3, a1 # E : 000000000000chch
38 andnot a0, 7, v0 # E : align our loop pointer
39 lda t4, -1 # E : build garbage mask
42 or a2, a3, a2 # E : chch000000000000
43 inswl a1, 2, t5 # E : 00000000chch0000
44 inswl a1, 4, a3 # E : 0000chch00000000
46 or a1, a2, a1 # E : chch00000000chch
47 or a3, t5, t5 # E : 0000chchchch0000
48 cmpbge zero, t0, t2 # E : bits set iff byte == zero
[all …]
Dev6-stxncpy.S65 lda t2, -1 # E : build a mask against false zero
68 ornot t1, t2, t2 # E : (stall)
71 cmpbge zero, t2, t8 # E : bits set iff null found
72 or t0, t3, t0 # E : (stall)
90 addq a0, 8, a0 # E :
91 subq a2, 1, a2 # E :
95 addq a1, 8, a1 # E :
96 cmpbge zero, t0, t8 # E :
112 negq t8, t12 # E : find low bit set
113 and t8, t12, t12 # E : (stall)
[all …]
Dev67-strlen.S29 lda $2, -1($31) # E :
31 andnot $16, 7, $0 # E :
33 or $2, $1, $1 # E :
34 cmpbge $31, $1, $2 # E : $2 <- bitmask: bit i == 1 <==> i-th byte == 0
35 nop # E :
39 addq $0, 8, $0 # E : addr += 8
40 cmpbge $31, $1, $2 # E :
45 addq $0, $3, $0 # E :
46 subq $0, $16, $0 # E :
Dev67-strcat.S32 mov $16, $0 # E : set up return value
35 lda $2, -1 # E :
38 andnot $16, 7, $16 # E :
39 or $2, $1, $1 # E :
40 cmpbge $31, $1, $2 # E : bits set iff byte == 0
44 addq $16, 8, $16 # E :
45 cmpbge $31, $1, $2 # E :
49 addq $16, $3, $16 # E :
51 mov $26, $23 # E :
/arch/x86/crypto/
Daes-x86_64-asm_64.S58 movl (r7),r5 ## E; \
59 movl 4(r7),r1 ## E; \
60 movl 8(r7),r6 ## E; \
61 movl 12(r7),r7 ## E; \
62 movl 480(r8),r10 ## E; \
63 xorl -48(r9),r5 ## E; \
64 xorl -44(r9),r1 ## E; \
65 xorl -40(r9),r6 ## E; \
66 xorl -36(r9),r7 ## E; \
67 cmpl $24,r10 ## E; \
[all …]
Dsha1_ssse3_asm.S122 mov 16(HASH_PTR), E
132 RR F1,A,B,C,D,E,0
133 RR F1,D,E,A,B,C,2
134 RR F1,B,C,D,E,A,4
135 RR F1,E,A,B,C,D,6
136 RR F1,C,D,E,A,B,8
138 RR F1,A,B,C,D,E,10
139 RR F1,D,E,A,B,C,12
140 RR F1,B,C,D,E,A,14
141 RR F1,E,A,B,C,D,16
[all …]
Dsha1_avx2_x86_64_asm.S104 .set E, REG_E define
323 .set T_REG, E
324 .set E, D define
383 add WK(\r), E
386 lea (RE,RTB), E /* Add F from the previous round */
400 lea (RE,RTA), E /* E += A >>> 5 */
404 add WK(\r), E
405 lea (RE,RTB), E /* Add F from the previous round */
418 add TA, E /* E += A >>> 5 */
426 add WK(\r), E
[all …]
/arch/arm/crypto/
Dsha1-armv4-large.S75 add r7,r8,r7,ror#2 @ E+=K_00_19
80 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
84 add r7,r8,r7,ror#2 @ E+=K_00_19
86 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
92 add r7,r7,r9 @ E+=X[i]
95 add r7,r7,r10 @ E+=F_00_19(B,C,D)
100 add r6,r8,r6,ror#2 @ E+=K_00_19
105 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
109 add r6,r8,r6,ror#2 @ E+=K_00_19
111 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
[all …]
Dsha256-armv4.pl51 $E="r8";
55 @V=($A,$B,$C,$D,$E,$F,$G,$H);
224 ldmia $ctx,{$A,$B,$C,$D,$E,$F,$G,$H}
258 add $E,$E,$t1
265 stmia $t3,{$A,$B,$C,$D,$E,$F,$G,$H}
551 add $E,$E,$t0
559 stmia $t1,{$E-$H}
/arch/x86/crypto/sha-mb/
Dsha1_x8_avx2.S229 # ymm4 E
247 E = %ymm4 define
273 TMP_ = E
274 E = D define
313 vmovdqu 4*32(arg1), E
364 vmovdqu E,EE
373 SHA1_STEP_00_15 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
382 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F0
390 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F1
398 SHA1_STEP_16_79 A,B,C,D,E, TMP,FUN, I, K, MAGIC_F2
[all …]
/arch/m68k/hp300/
Dhp300map.map161 string F5 = "\033[[E"
201 compose 'A' 'E' to '�'
205 compose '`' 'E' to '�'
207 compose '\'' 'E' to '�'
209 compose '^' 'E' to '�'
211 compose '"' 'E' to '�'
/arch/arm/boot/dts/
Domap3-igep0030.dts2 * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
15 model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
/arch/cris/arch-v32/lib/
Dstrcmp.S3 ; Written by Edgar E. Iglesias
/arch/arm/mach-cns3xxx/
DKconfig17 for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
/arch/mips/vr41xx/
DPlatform8 # CASIO CASSIPEIA E-55/65 (VR4111)

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