Searched refs:cchip (Results 1 – 2 of 2) sorted by relevance
62 register titan_cchip *cchip = TITAN_cchip; in titan_update_irq_hw() local83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
49 register tsunami_cchip *cchip = TSUNAMI_cchip; in tsunami_update_irq_hw() local68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()