Searched refs:cntval_mask (Results 1 – 9 of 9) sorted by relevance
225 .cntval_mask = (1ULL << 32) - 1,
307 .cntval_mask = (1ULL << 40) - 1,
638 .cntval_mask = (1ULL << 48) - 1,
1143 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()1153 (u64)(-left) & x86_pmu.cntval_mask); in x86_perf_event_set_period()1758 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); in init_hw_perf_events()
528 u64 cntval_mask; member
1322 .cntval_mask = ARCH_P4_CNTRVAL_MASK,
850 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
3268 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()3640 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in intel_pmu_init()
75 u64 cntval_mask; /* counter width mask */ member336 .cntval_mask = (1ULL << 32) - 1,581 write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask); in tile_event_set_period()