Home
last modified time | relevance | path

Searched refs:op2 (Results 1 – 18 of 18) sorted by relevance

/arch/m32r/kernel/
Dptrace.c259 unsigned long op, op2, op3; in compute_next_pc_for_16bit_insn() local
272 op2 = (insn >> 8) & 0xf; in compute_next_pc_for_16bit_insn()
276 switch (op2) { in compute_next_pc_for_16bit_insn()
301 switch (op2) { in compute_next_pc_for_16bit_insn()
363 unsigned long op2; in compute_next_pc_for_32bit_insn() local
369 op2 = (insn >> 24) & 0xf; in compute_next_pc_for_32bit_insn()
370 switch (op2) { in compute_next_pc_for_32bit_insn()
394 op2 = (insn >> 20) & 0xf; in compute_next_pc_for_32bit_insn()
395 switch (op2) { in compute_next_pc_for_32bit_insn()
406 if (check_condition_src(op2, regno1, regno2, child)) { in compute_next_pc_for_32bit_insn()
/arch/sh/kernel/
Dkprobes.c152 struct kprobe *op1, *op2; in prepare_singlestep() local
157 op2 = this_cpu_ptr(&saved_next_opcode2); in prepare_singlestep()
181 op2->addr = in prepare_singlestep()
183 op2->opcode = *(op2->addr); in prepare_singlestep()
184 arch_arm_kprobe(op2); in prepare_singlestep()
191 op2->addr = in prepare_singlestep()
193 op2->opcode = *(op2->addr); in prepare_singlestep()
194 arch_arm_kprobe(op2); in prepare_singlestep()
/arch/arm/include/asm/
Datomic.h278 #define ATOMIC64_OP(op, op1, op2) \ argument
288 " " #op2 " %R0, %R0, %R4\n" \
297 #define ATOMIC64_OP_RETURN(op, op1, op2) \ argument
309 " " #op2 " %R0, %R0, %R4\n" \
320 #define ATOMIC64_OPS(op, op1, op2) \ argument
321 ATOMIC64_OP(op, op1, op2) \
322 ATOMIC64_OP_RETURN(op, op1, op2)
/arch/x86/crypto/
Dcast6-avx-x86_64-asm_64.S99 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
108 op2 s3(, RID1, 4), dst ## d; \
125 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
126 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
127 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
129 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
132 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
139 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
143 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
144 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
Dcast5-avx-x86_64-asm_64.S99 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument
108 op2 s3(, RID1, 4), dst ## d; \
125 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument
126 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \
127 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \
129 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \
132 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \
139 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument
143 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
144 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
Dtwofish-x86_64-asm_64-3way.S92 #define do16bit_ror(rot, op1, op2, T0, T1, tmp1, tmp2, ab, dst) \ argument
97 op2##l T1(CTX, tmp1, 4), dst ## d;
/arch/powerpc/math-emu/
Dmath.c27 #define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \
227 void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0; in do_mathemu() local
333 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
339 op2 = (void *)&current->thread.TS_FPR((insn >> 6) & 0x1f); in do_mathemu()
345 op2 = (void *)&current->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu()
399 op2 = (void *)&current->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu()
406 op2 = (void *)((insn >> 18) & 0x7); in do_mathemu()
434 eflag = func(op0, op1, op2, op3); in do_mathemu()
/arch/arm64/include/asm/
Desr.h136 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
139 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
Dsysreg.h37 #define sys_reg(op0, op1, crn, crm, op2) \ argument
38 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
/arch/s390/net/
Dbpf_jit_comp.c196 #define _EMIT6(op1, op2) \ argument
200 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \
205 #define _EMIT6_DISP(op1, op2, disp) \ argument
208 _EMIT6(op1 | __disp, op2); \
211 #define _EMIT6_DISP_LH(op1, op2, disp) \ argument
216 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \
219 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ argument
222 reg_high(b3) << 8, op2, disp); \
228 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ argument
232 op2 | mask << 12); \
[all …]
/arch/arm64/include/uapi/asm/
Dkvm.h181 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
187 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
/arch/arm/include/uapi/asm/
Dkvm.h128 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
133 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
/arch/s390/include/asm/
Dpercpu.h65 #define arch_this_cpu_add(pcp, val, op1, op2, szcast) \ argument
75 op2 " %[ptr__],%[val__]\n" \
/arch/s390/kvm/
Dpriv.c38 u64 op2, val; in handle_set_clock() local
43 op2 = kvm_s390_get_base_disp_s(vcpu, &ar); in handle_set_clock()
44 if (op2 & 7) /* Operand must be on a doubleword boundary */ in handle_set_clock()
46 rc = read_guest(vcpu, op2, ar, &val, sizeof(val)); in handle_set_clock()
/arch/arm/include/asm/hardware/
Dcp14.h25 #define MRC14(op1, crn, crm, op2) \ argument
28 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
32 #define MCR14(val, op1, crn, crm, op2) \ argument
34 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
/arch/arm/kvm/
Dcoproc.c605 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \ argument
614 ", " __stringify(op2) "\n" : "=r" (val)); \
/arch/m68k/fpsp040/
Dbugfix.S195 bne op2sgl |not opclass 0, check op2
/arch/m68k/ifpsp060/src/
Dfpsp.S15848 # FP_DST(a6) = fp op2(dst) #
15852 # FP_DST(a6) = fp op2 scaled(dst) #