| /arch/x86/kernel/cpu/ |
| D | centaur.c | 31 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
39 wrmsr(MSR_VIA_RNG, lo, hi); in init_c3()
53 wrmsr(MSR_VIA_FCR, lo, hi); in init_c3()
168 wrmsr(MSR_IDT_FCR1, newlo, hi); in init_centaur()
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| D | transmeta.c | 84 wrmsr(0x80860004, ~0, uk); in init_transmeta()
86 wrmsr(0x80860004, cap_mask, uk); in init_transmeta()
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| D | amd.c | 156 wrmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
177 wrmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
223 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); in init_amd_k7()
1063 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); in set_dr_addr_mask()
1068 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); in set_dr_addr_mask()
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| D | perf_event_intel_cqm.c | 107 wrmsr(MSR_IA32_QM_EVTSEL, QOS_L3_OCCUP_EVENT_ID, rmid); in __rmid_read()
1025 wrmsr(MSR_IA32_PQR_ASSOC, rmid, state->closid); in intel_cqm_event_start()
1041 wrmsr(MSR_IA32_PQR_ASSOC, 0, state->closid); in intel_cqm_event_stop()
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| D | common.c | 265 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); in squash_the_stupid_serial_number()
1328 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); in enable_sep_cpu()
1330 wrmsr(MSR_IA32_SYSENTER_ESP, in enable_sep_cpu()
1334 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); in enable_sep_cpu()
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| /arch/x86/kernel/cpu/mcheck/ |
| D | therm_throt.c | 525 wrmsr(MSR_IA32_THERM_INTERRUPT, in intel_init_thermal()
529 wrmsr(MSR_IA32_THERM_INTERRUPT, in intel_init_thermal()
533 wrmsr(MSR_IA32_THERM_INTERRUPT, in intel_init_thermal()
539 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, in intel_init_thermal()
544 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, in intel_init_thermal()
549 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, in intel_init_thermal()
557 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); in intel_init_thermal()
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| D | winchip.c | 38 wrmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| D | mce_amd.c | 193 wrmsr(tr->b->address, lo, hi); in threshold_restart_bank()
247 wrmsr(MSR_CU_DEF_ERR, low, high); in deferred_error_interrupt_enable()
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| /arch/x86/oprofile/ |
| D | op_model_p4.c | 545 wrmsr(ev->bindings[i].escr_address, escr, high); in pmc_setup_one_p4_counter()
557 wrmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address, in pmc_setup_one_p4_counter()
591 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_setup_ctrs()
598 wrmsr(msrs->controls[i].addr, 0, 0); in p4_setup_ctrs()
654 wrmsr(p4_counters[real].cccr_address, low, high); in p4_check_ctrs()
680 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_start()
697 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_stop()
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| /arch/x86/include/asm/ |
| D | msr.h | 192 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) in wrmsr() function
248 #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high))
250 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
278 wrmsr(msr_no, l, h); in wrmsr_on_cpu()
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| D | apic.h | 177 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); in native_apic_msr_write()
182 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); in native_apic_msr_eoi_write()
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| D | paravirt.h | 151 #define wrmsr(msr, val1, val2) \ macro
164 wrmsr(msr, (u32)val, (u32)(val>>32)); in wrmsrl()
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| D | processor.h | 479 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); in native_load_sp0()
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| /arch/x86/realmode/rm/ |
| D | wakeup_asm.S | 103 wrmsr
123 wrmsr
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| D | reboot.S | 39 wrmsr
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| /arch/x86/kernel/ |
| D | verify_cpu.S | 99 wrmsr
130 wrmsr
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| D | head_64.S | 210 1: wrmsr /* Make changes effective */
259 wrmsr
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| /arch/x86/boot/compressed/ |
| D | efi_thunk_64.S | 133 wrmsr
160 wrmsr
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| D | head_64.S | 171 wrmsr
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| /arch/x86/kernel/cpu/mtrr/ |
| D | amd.c | 91 wrmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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| D | centaur.c | 95 wrmsr(MSR_IDT_MCR0 + reg, low, high); in centaur_set_mcr()
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| /arch/x86/lib/ |
| D | msr-reg.S | 91 op_safe_regs wrmsr
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| D | msr-smp.c | 31 wrmsr(rv->msr_no, reg->l, reg->h); in __wrmsr_on_cpu()
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| /arch/x86/xen/ |
| D | xen-head.S | 78 1: wrmsr
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| /arch/x86/kernel/apic/ |
| D | apic.c | 1109 wrmsr(MSR_IA32_APICBASE, l, h); in disable_local_APIC()
1738 wrmsr(MSR_IA32_APICBASE, l, h); in apic_force_enable()
2403 wrmsr(MSR_IA32_APICBASE, l, h); in lapic_resume()
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