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Searched refs:F (Results 1 – 25 of 48) sorted by relevance

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/drivers/gpu/drm/i915/
Di915_cmd_parser.c105 #define F true macro
114 CMD( MI_NOOP, SMI, F, 1, S ),
115 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ),
116 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ),
117 CMD( MI_ARB_CHECK, SMI, F, 1, S ),
118 CMD( MI_REPORT_HEAD, SMI, F, 1, S ),
119 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
120 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
121 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
122 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
[all …]
/drivers/clk/qcom/
Dgcc-msm8916.c267 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } macro
402 F(40000000, P_GPLL0, 10, 1, 2),
403 F(80000000, P_GPLL0, 10, 0, 0),
422 F(19200000, P_XO, 1, 0, 0),
423 F(50000000, P_GPLL0, 16, 0, 0),
424 F(100000000, P_GPLL0, 8, 0, 0),
425 F(133330000, P_GPLL0, 6, 0, 0),
443 F(100000000, P_GPLL0, 8, 0, 0),
444 F(200000000, P_GPLL0, 4, 0, 0),
475 F(19200000, P_XO, 1, 0, 0),
[all …]
Dmmcc-msm8974.c187 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } macro
287 F( 19200000, P_XO, 1, 0, 0),
288 F( 37500000, P_GPLL0, 16, 0, 0),
289 F( 50000000, P_GPLL0, 12, 0, 0),
290 F( 75000000, P_GPLL0, 8, 0, 0),
291 F(100000000, P_GPLL0, 6, 0, 0),
292 F(150000000, P_GPLL0, 4, 0, 0),
293 F(291750000, P_MMPLL1, 4, 0, 0),
294 F(400000000, P_MMPLL0, 2, 0, 0),
295 F(466800000, P_MMPLL1, 2.5, 0, 0),
[all …]
Dmmcc-apq8084.c222 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } macro
337 F(19200000, P_XO, 1, 0, 0),
338 F(37500000, P_GPLL0, 16, 0, 0),
339 F(50000000, P_GPLL0, 12, 0, 0),
340 F(75000000, P_GPLL0, 8, 0, 0),
341 F(100000000, P_GPLL0, 6, 0, 0),
342 F(150000000, P_GPLL0, 4, 0, 0),
343 F(333430000, P_MMPLL1, 3.5, 0, 0),
344 F(400000000, P_MMPLL0, 2, 0, 0),
345 F(466800000, P_MMPLL1, 2.5, 0, 0),
[all …]
Dgcc-msm8974.c65 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } macro
185 F(125000000, P_GPLL0, 1, 5, 24),
204 F(19200000, P_XO, 1, 0, 0),
205 F(37500000, P_GPLL0, 16, 0, 0),
206 F(50000000, P_GPLL0, 12, 0, 0),
224 F(960000, P_XO, 10, 1, 2),
225 F(4800000, P_XO, 4, 0, 0),
226 F(9600000, P_XO, 2, 0, 0),
227 F(15000000, P_GPLL0, 10, 1, 4),
228 F(19200000, P_XO, 1, 0, 0),
[all …]
Dgcc-apq8084.c109 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } macro
229 F(100000000, P_GPLL0, 6, 0, 0),
230 F(200000000, P_GPLL0, 3, 0, 0),
231 F(240000000, P_GPLL0, 2.5, 0, 0),
250 F(125000000, P_GPLL0, 1, 5, 24),
269 F(125000000, P_GPLL0, 1, 5, 24),
322 F(19200000, P_XO, 1, 0, 0),
323 F(50000000, P_GPLL0, 12, 0, 0),
341 F(960000, P_XO, 10, 1, 2),
342 F(4800000, P_XO, 4, 0, 0),
[all …]
/drivers/video/fbdev/kyro/
DSTG4000InitDevice.c121 u32 R = 0, F = 0, OD = 0, ODIndex = 0; in ProgramClock() local
153 F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER)); in ProgramClock()
156 if (F > STG4K3_PLL_MIN_F) in ProgramClock()
157 F--; in ProgramClock()
165 while ((F >= STG4K3_PLL_MIN_F) && in ProgramClock()
166 (F <= STG4K3_PLL_MAX_F)) { in ProgramClock()
169 ulVCO = F * ulVCO; in ProgramClock()
194 ulBestF = F; in ProgramClock()
211 ulBestF = F; in ProgramClock()
219 F++; in ProgramClock()
[all …]
DSTG4000Ramdac.c30 u32 F = 0, R = 0, P = 0; in InitialiseRamdac() local
87 *pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P); in InitialiseRamdac()
93 tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); in InitialiseRamdac()
/drivers/media/dvb-frontends/
Dcx24113.c305 s64 F; in cx24113_calc_pll_nf() local
347 F = freq_hz; in cx24113_calc_pll_nf()
348 F *= (u64) (R * vcodiv * 262144); in cx24113_calc_pll_nf()
349 dprintk("1 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
351 dividend = F; in cx24113_calc_pll_nf()
353 F = dividend; in cx24113_calc_pll_nf()
354 dprintk("2 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
355 F -= (N + 32) * 262144; in cx24113_calc_pll_nf()
357 dprintk("3 N: %d, F: %lld, R: %d\n", N, (long long)F, R); in cx24113_calc_pll_nf()
360 if (F > (262144 / 2 - 1638)) in cx24113_calc_pll_nf()
[all …]
/drivers/net/ethernet/sfc/
Dnic.c189 #define REGISTER_AA(name) REGISTER(name, F, A, A)
190 #define REGISTER_AB(name) REGISTER(name, F, A, B)
191 #define REGISTER_AZ(name) REGISTER(name, F, A, Z)
192 #define REGISTER_BB(name) REGISTER(name, F, B, B)
193 #define REGISTER_BZ(name) REGISTER(name, F, B, Z)
194 #define REGISTER_CZ(name) REGISTER(name, F, C, Z)
325 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
326 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
327 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
328 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
[all …]
/drivers/staging/unisys/
DMAINTAINERS4 F: Documentation/s-Par/overview.txt
5 F: Documentation/s-Par/proc-entries.txt
6 F: drivers/staging/unisys/
/drivers/pinctrl/sunxi/
Dpinctrl-sun5i-a13.c306 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun8i-a83t.c402 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
Dpinctrl-sun8i-a33.c336 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
361 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun8i-a23.c414 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
419 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
429 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
434 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
439 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun5i-a10s.c548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun9i-a80.c509 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
513 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
522 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
526 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
531 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun6i-a31s.c570 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
575 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
590 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
595 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun6i-a31.c652 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
662 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
667 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
672 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
677 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun4i-a10.c559 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Dpinctrl-sun7i-a20.c578 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
588 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
593 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
/drivers/ata/
Dpata_pdc2027x.c525 int F, R; in pdc_adjust_pll() local
565 F = (ratio * (R+2)) / 1000 - 2; in pdc_adjust_pll()
567 if (unlikely(F < 0 || F > 127)) { in pdc_adjust_pll()
569 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F); in pdc_adjust_pll()
573 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio); in pdc_adjust_pll()
575 pll_ctl = (R << 8) | F; in pdc_adjust_pll()
/drivers/net/dsa/
DKconfig21 tristate "Marvell 88E6085/6095/6095F/6131 ethernet switch chip support"
27 This enables support for the Marvell 88E6085/6095/6095F/6131
/drivers/staging/xgifb/
DXGI_main_26.c95 int B, C, D, F, temp, j; in XGIfb_mode_rate_to_ddata() local
112 F = HRS - HDE - 3; in XGIfb_mode_rate_to_ddata()
130 temp = HRE - ((HDE + F + 3) & 63); in XGIfb_mode_rate_to_ddata()
133 D = B - F - C; in XGIfb_mode_rate_to_ddata()
136 *right_margin = F * 8; in XGIfb_mode_rate_to_ddata()
151 F = VRS + 1 - VDE; in XGIfb_mode_rate_to_ddata()
164 temp = VRE - ((VDE + F - 1) & 31); in XGIfb_mode_rate_to_ddata()
167 D = B - F - C; in XGIfb_mode_rate_to_ddata()
170 *lower_margin = F; in XGIfb_mode_rate_to_ddata()
/drivers/staging/unisys/include/
Dchannel.h38 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
39 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))

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