Searched refs:gfx (Results 1 – 18 of 18) sorted by relevance
928 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()931 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()936 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()939 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()944 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()947 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()952 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()955 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()961 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()964 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()[all …]
612 adev->gfx.scratch.num_reg = 7; in gfx_v8_0_scratch_init()613 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v8_0_scratch_init()614 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { in gfx_v8_0_scratch_init()615 adev->gfx.scratch.free[i] = true; in gfx_v8_0_scratch_init()616 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; in gfx_v8_0_scratch_init()757 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v8_0_init_microcode()760 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v8_0_init_microcode()763 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v8_0_init_microcode()764 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v8_0_init_microcode()765 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v8_0_init_microcode()[all …]
44 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { in amdgpu_gfx_scratch_get()45 if (adev->gfx.scratch.free[i]) { in amdgpu_gfx_scratch_get()46 adev->gfx.scratch.free[i] = false; in amdgpu_gfx_scratch_get()47 *reg = adev->gfx.scratch.reg[i]; in amdgpu_gfx_scratch_get()66 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { in amdgpu_gfx_scratch_free()67 if (adev->gfx.scratch.reg[i] == reg) { in amdgpu_gfx_scratch_free()68 adev->gfx.scratch.free[i] = true; in amdgpu_gfx_scratch_free()
207 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in amdgpu_info_ioctl()208 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); in amdgpu_info_ioctl()214 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_info_ioctl()215 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); in amdgpu_info_ioctl()314 fw_info.ver = adev->gfx.me_fw_version; in amdgpu_info_ioctl()315 fw_info.feature = adev->gfx.me_feature_version; in amdgpu_info_ioctl()318 fw_info.ver = adev->gfx.pfp_fw_version; in amdgpu_info_ioctl()319 fw_info.feature = adev->gfx.pfp_feature_version; in amdgpu_info_ioctl()322 fw_info.ver = adev->gfx.ce_fw_version; in amdgpu_info_ioctl()323 fw_info.feature = adev->gfx.ce_feature_version; in amdgpu_info_ioctl()[all …]
496 adev->gfx.pfp_fw->data; in get_fw_version()501 adev->gfx.me_fw->data; in get_fw_version()506 adev->gfx.ce_fw->data; in get_fw_version()511 adev->gfx.mec_fw->data; in get_fw_version()516 adev->gfx.mec2_fw->data; in get_fw_version()521 adev->gfx.rlc_fw->data; in get_fw_version()
643 adev->gfx.pfp_fw->data; in get_fw_version()648 adev->gfx.me_fw->data; in get_fw_version()653 adev->gfx.ce_fw->data; in get_fw_version()658 adev->gfx.mec_fw->data; in get_fw_version()663 adev->gfx.mec2_fw->data; in get_fw_version()668 adev->gfx.rlc_fw->data; in get_fw_version()
89 if (ring < adev->gfx.num_gfx_rings) { in amdgpu_cs_get_ring()90 *out_ring = &adev->gfx.gfx_ring[ring]; in amdgpu_cs_get_ring()93 adev->gfx.num_gfx_rings); in amdgpu_cs_get_ring()98 if (ring < adev->gfx.num_compute_rings) { in amdgpu_cs_get_ring()99 *out_ring = &adev->gfx.compute_ring[ring]; in amdgpu_cs_get_ring()102 adev->gfx.num_compute_rings); in amdgpu_cs_get_ring()
521 static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);522 static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);523 static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
113 struct gfx_firmware_header_v1_0 gfx; member
303 if (ring == &adev->gfx.gfx_ring[0]) { in amdgpu_ib_ring_tests()
1176 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) { in cz_enable_didt()1182 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE; in cz_enable_didt()1192 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) { in cz_enable_didt()1198 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in cz_enable_didt()
1420 mutex_init(&adev->gfx.gpu_clock_mutex); in amdgpu_device_init()
2072 struct amdgpu_gfx gfx; member
29 __u8 *gfx; member251 saved->gfx[i] = vga_rgfx(state->vgabase, i); in save_vga_mode()291 vga_wgfx(state->vgabase, i, saved->gfx[i]); in restore_vga_mode()390 saved->gfx = saved->crtc + state->num_crtc; in save_vga()391 saved->seq = saved->gfx + state->num_gfx; in save_vga()
214 struct gfx_firmware_header_v1_0 gfx; member
65 usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll, enumerator
64 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll, enumerator
1759 unsigned long temp, chipset, gfx; in i915_emon_status() local1771 gfx = i915_gfx_val(dev_priv); in i915_emon_status()1776 seq_printf(m, "GFX power: %ld\n", gfx); in i915_emon_status()1777 seq_printf(m, "Total power: %ld\n", chipset + gfx); in i915_emon_status()