| /drivers/gpu/drm/nouveau/ |
| D | nouveau_dp.c | 69 nv_encoder->dp.link_bw = 27000 * dpcd[1]; in nouveau_dp_detect()
73 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); in nouveau_dp_detect()
76 nv_encoder->dcb->dpconf.link_bw); in nouveau_dp_detect()
80 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) in nouveau_dp_detect()
81 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; in nouveau_dp_detect()
84 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); in nouveau_dp_detect()
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| D | nouveau_encoder.h | 62 int link_bw; member
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| D | nouveau_bios.c | 1479 entry->dpconf.link_bw = 162000; in parse_dcb20_entry()
1482 entry->dpconf.link_bw = 270000; in parse_dcb20_entry()
1485 entry->dpconf.link_bw = 540000; in parse_dcb20_entry()
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| D | nouveau_connector.c | 875 max_clock *= nv_encoder->dp.link_bw; in nouveau_connector_mode_valid()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dport.c | 40 u32 link_bw; member
67 OUTP_DBG(&outp->base, "%d lanes at %d KB/s", dp->link_nr, dp->link_bw); in dp_set_link_config()
72 while ((dp->link_bw / 10) < nvbios_rd16(bios, lnkcmp)) in dp_set_link_config()
76 while ((dp->link_bw / 27000) < nvbios_rd08(bios, lnkcmp)) in dp_set_link_config()
84 ret = outp->func->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, in dp_set_link_config()
96 sink[0] = dp->link_bw / 27000; in dp_set_link_config()
344 if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) in nvkm_dp_train()
345 outp->dpcd[1] = outp->base.info.dpconf.link_bw; in nvkm_dp_train()
376 dp->link_bw = cfg->bw * 27000; in nvkm_dp_train()
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| D | gf119.c | 256 u32 datarate, link_nr, link_bw, bits; in gf119_disp_intr_unk2_2_tu() local
260 link_bw = (clksor & 0x007c0000) >> 18; in gf119_disp_intr_unk2_2_tu()
261 link_bw *= 27000; in gf119_disp_intr_unk2_2_tu()
265 value = value * link_bw; in gf119_disp_intr_unk2_2_tu()
272 value = value * link_bw; in gf119_disp_intr_unk2_2_tu()
285 do_div(ratio, link_nr * link_bw); in gf119_disp_intr_unk2_2_tu()
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| D | nv50.c | 505 u32 link_nr, link_bw, bits; in nv50_disp_intr_unk20_2_dp() local
508 link_bw = (clksor & 0x000c0000) ? 270000 : 162000; in nv50_disp_intr_unk20_2_dp()
513 value = value * link_bw; in nv50_disp_intr_unk20_2_dp()
520 value = value * link_bw; in nv50_disp_intr_unk20_2_dp()
534 do_div(link_ratio, link_bw); in nv50_disp_intr_unk20_2_dp()
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| D | outpdp.c | 87 outp->base.info.dpconf.link_bw; in nvkm_output_dp_train()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | dcb.c | 147 outp->dpconf.link_bw = 0x06; in dcb_outp_parse()
150 outp->dpconf.link_bw = 0x0a; in dcb_outp_parse()
154 outp->dpconf.link_bw = 0x14; in dcb_outp_parse()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| D | anx9805.c | 193 int link_nr, int link_bw, bool enh) in anx9805_aux_lnk_ctl() argument
201 link_nr, link_bw, enh); in anx9805_aux_lnk_ctl()
203 nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw); in anx9805_aux_lnk_ctl()
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| D | aux.h | 8 int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw,
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| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 263 uint8_t link_bw; member
358 cdv_intel_dp_link_clock(uint8_t link_bw) in cdv_intel_dp_link_clock() argument
360 if (link_bw == DP_LINK_BW_2_7) in cdv_intel_dp_link_clock()
918 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup()
920 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
923 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
932 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
933 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
936 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
1072 intel_dp->link_configuration[0] = intel_dp->link_bw; in cdv_intel_dp_mode_set()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | dcb.h | 47 int link_bw; member
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | i2c.h | 70 int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
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| /drivers/gpu/drm/ |
| D | drm_dp_helper.c | 148 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
150 switch (link_bw) { in drm_dp_bw_code_to_link_rate()
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| /drivers/gpu/drm/i915/ |
| D | intel_dp.c | 1366 uint8_t *link_bw, uint8_t *rate_select) in intel_dp_compute_rate() argument
1369 *link_bw = 0; in intel_dp_compute_rate()
1373 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1399 uint8_t link_bw, rate_select; in intel_dp_compute_config() local
1508 &link_bw, &rate_select); in intel_dp_compute_config()
1511 link_bw, rate_select, pipe_config->lane_count, in intel_dp_compute_config()
3699 uint8_t link_bw, rate_select; in intel_dp_link_training_clock_recovery() local
3705 &link_bw, &rate_select); in intel_dp_link_training_clock_recovery()
3708 link_config[0] = link_bw; in intel_dp_link_training_clock_recovery()
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| D | intel_drv.h | 1057 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
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| D | intel_display.c | 6574 int lane, link_bw, fdi_dotclock, ret; in ironlake_fdi_compute_config() local
6585 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; in ironlake_fdi_compute_config()
6589 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, in ironlake_fdi_compute_config()
6595 link_bw, &pipe_config->fdi_m_n); in ironlake_fdi_compute_config()
8821 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) in ironlake_get_lanes_required() argument
8829 return DIV_ROUND_UP(bps, link_bw * 8); in ironlake_get_lanes_required()
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