1 #ifndef __ASM_MACH_IRQS_H 2 #define __ASM_MACH_IRQS_H 3 4 /* 5 * Interrupt numbers for PXA168 6 */ 7 #define IRQ_PXA168_NONE (-1) 8 #define IRQ_PXA168_SSP4 0 9 #define IRQ_PXA168_SSP3 1 10 #define IRQ_PXA168_SSP2 2 11 #define IRQ_PXA168_SSP1 3 12 #define IRQ_PXA168_PMIC_INT 4 13 #define IRQ_PXA168_RTC_INT 5 14 #define IRQ_PXA168_RTC_ALARM 6 15 #define IRQ_PXA168_TWSI0 7 16 #define IRQ_PXA168_GPU 8 17 #define IRQ_PXA168_KEYPAD 9 18 #define IRQ_PXA168_ONEWIRE 12 19 #define IRQ_PXA168_TIMER1 13 20 #define IRQ_PXA168_TIMER2 14 21 #define IRQ_PXA168_TIMER3 15 22 #define IRQ_PXA168_CMU 16 23 #define IRQ_PXA168_SSP5 17 24 #define IRQ_PXA168_MSP_WAKEUP 19 25 #define IRQ_PXA168_CF_WAKEUP 20 26 #define IRQ_PXA168_XD_WAKEUP 21 27 #define IRQ_PXA168_MFU 22 28 #define IRQ_PXA168_MSP 23 29 #define IRQ_PXA168_CF 24 30 #define IRQ_PXA168_XD 25 31 #define IRQ_PXA168_DDR_INT 26 32 #define IRQ_PXA168_UART1 27 33 #define IRQ_PXA168_UART2 28 34 #define IRQ_PXA168_UART3 29 35 #define IRQ_PXA168_WDT 35 36 #define IRQ_PXA168_MAIN_PMU 36 37 #define IRQ_PXA168_FRQ_CHANGE 38 38 #define IRQ_PXA168_SDH1 39 39 #define IRQ_PXA168_SDH2 40 40 #define IRQ_PXA168_LCD 41 41 #define IRQ_PXA168_CI 42 42 #define IRQ_PXA168_USB1 44 43 #define IRQ_PXA168_NAND 45 44 #define IRQ_PXA168_HIFI_DMA 46 45 #define IRQ_PXA168_DMA_INT0 47 46 #define IRQ_PXA168_DMA_INT1 48 47 #define IRQ_PXA168_GPIOX 49 48 #define IRQ_PXA168_USB2 51 49 #define IRQ_PXA168_AC97 57 50 #define IRQ_PXA168_TWSI1 58 51 #define IRQ_PXA168_AP_PMU 60 52 #define IRQ_PXA168_SM_INT 63 53 54 /* 55 * Interrupt numbers for PXA910 56 */ 57 #define IRQ_PXA910_NONE (-1) 58 #define IRQ_PXA910_AIRQ 0 59 #define IRQ_PXA910_SSP3 1 60 #define IRQ_PXA910_SSP2 2 61 #define IRQ_PXA910_SSP1 3 62 #define IRQ_PXA910_PMIC_INT 4 63 #define IRQ_PXA910_RTC_INT 5 64 #define IRQ_PXA910_RTC_ALARM 6 65 #define IRQ_PXA910_TWSI0 7 66 #define IRQ_PXA910_GPU 8 67 #define IRQ_PXA910_KEYPAD 9 68 #define IRQ_PXA910_ROTARY 10 69 #define IRQ_PXA910_TRACKBALL 11 70 #define IRQ_PXA910_ONEWIRE 12 71 #define IRQ_PXA910_AP1_TIMER1 13 72 #define IRQ_PXA910_AP1_TIMER2 14 73 #define IRQ_PXA910_AP1_TIMER3 15 74 #define IRQ_PXA910_IPC_AP0 16 75 #define IRQ_PXA910_IPC_AP1 17 76 #define IRQ_PXA910_IPC_AP2 18 77 #define IRQ_PXA910_IPC_AP3 19 78 #define IRQ_PXA910_IPC_AP4 20 79 #define IRQ_PXA910_IPC_CP0 21 80 #define IRQ_PXA910_IPC_CP1 22 81 #define IRQ_PXA910_IPC_CP2 23 82 #define IRQ_PXA910_IPC_CP3 24 83 #define IRQ_PXA910_IPC_CP4 25 84 #define IRQ_PXA910_L2_DDR 26 85 #define IRQ_PXA910_UART2 27 86 #define IRQ_PXA910_UART3 28 87 #define IRQ_PXA910_AP2_TIMER1 29 88 #define IRQ_PXA910_AP2_TIMER2 30 89 #define IRQ_PXA910_CP2_TIMER1 31 90 #define IRQ_PXA910_CP2_TIMER2 32 91 #define IRQ_PXA910_CP2_TIMER3 33 92 #define IRQ_PXA910_GSSP 34 93 #define IRQ_PXA910_CP2_WDT 35 94 #define IRQ_PXA910_MAIN_PMU 36 95 #define IRQ_PXA910_CP_FREQ_CHG 37 96 #define IRQ_PXA910_AP_FREQ_CHG 38 97 #define IRQ_PXA910_MMC 39 98 #define IRQ_PXA910_AEU 40 99 #define IRQ_PXA910_LCD 41 100 #define IRQ_PXA910_CCIC 42 101 #define IRQ_PXA910_IRE 43 102 #define IRQ_PXA910_USB1 44 103 #define IRQ_PXA910_NAND 45 104 #define IRQ_PXA910_HIFI_DMA 46 105 #define IRQ_PXA910_DMA_INT0 47 106 #define IRQ_PXA910_DMA_INT1 48 107 #define IRQ_PXA910_AP_GPIO 49 108 #define IRQ_PXA910_AP2_TIMER3 50 109 #define IRQ_PXA910_USB2 51 110 #define IRQ_PXA910_TWSI1 54 111 #define IRQ_PXA910_CP_GPIO 55 112 #define IRQ_PXA910_UART1 59 /* Slow UART */ 113 #define IRQ_PXA910_AP_PMU 60 114 #define IRQ_PXA910_SM_INT 63 /* from PinMux */ 115 116 /* 117 * Interrupt numbers for MMP2 118 */ 119 #define IRQ_MMP2_NONE (-1) 120 #define IRQ_MMP2_SSP1 0 121 #define IRQ_MMP2_SSP2 1 122 #define IRQ_MMP2_SSPA1 2 123 #define IRQ_MMP2_SSPA2 3 124 #define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ 125 #define IRQ_MMP2_RTC_MUX 5 126 #define IRQ_MMP2_TWSI1 7 127 #define IRQ_MMP2_GPU 8 128 #define IRQ_MMP2_KEYPAD_MUX 9 129 #define IRQ_MMP2_ROTARY 10 130 #define IRQ_MMP2_TRACKBALL 11 131 #define IRQ_MMP2_ONEWIRE 12 132 #define IRQ_MMP2_TIMER1 13 133 #define IRQ_MMP2_TIMER2 14 134 #define IRQ_MMP2_TIMER3 15 135 #define IRQ_MMP2_RIPC 16 136 #define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ 137 #define IRQ_MMP2_HDMI 19 138 #define IRQ_MMP2_SSP3 20 139 #define IRQ_MMP2_SSP4 21 140 #define IRQ_MMP2_USB_HS1 22 141 #define IRQ_MMP2_USB_HS2 23 142 #define IRQ_MMP2_UART3 24 143 #define IRQ_MMP2_UART1 27 144 #define IRQ_MMP2_UART2 28 145 #define IRQ_MMP2_MIPI_DSI 29 146 #define IRQ_MMP2_CI2 30 147 #define IRQ_MMP2_PMU_TIMER1 31 148 #define IRQ_MMP2_PMU_TIMER2 32 149 #define IRQ_MMP2_PMU_TIMER3 33 150 #define IRQ_MMP2_USB_FS 34 151 #define IRQ_MMP2_MISC_MUX 35 152 #define IRQ_MMP2_WDT1 36 153 #define IRQ_MMP2_NAND_DMA 37 154 #define IRQ_MMP2_USIM 38 155 #define IRQ_MMP2_MMC 39 156 #define IRQ_MMP2_WTM 40 157 #define IRQ_MMP2_LCD 41 158 #define IRQ_MMP2_CI 42 159 #define IRQ_MMP2_IRE 43 160 #define IRQ_MMP2_USB_OTG 44 161 #define IRQ_MMP2_NAND 45 162 #define IRQ_MMP2_UART4 46 163 #define IRQ_MMP2_DMA_FIQ 47 164 #define IRQ_MMP2_DMA_RIQ 48 165 #define IRQ_MMP2_GPIO 49 166 #define IRQ_MMP2_MIPI_HSI1_MUX 51 167 #define IRQ_MMP2_MMC2 52 168 #define IRQ_MMP2_MMC3 53 169 #define IRQ_MMP2_MMC4 54 170 #define IRQ_MMP2_MIPI_HSI0_MUX 55 171 #define IRQ_MMP2_MSP 58 172 #define IRQ_MMP2_MIPI_SLIM_DMA 59 173 #define IRQ_MMP2_PJ4_FREQ_CHG 60 174 #define IRQ_MMP2_MIPI_SLIM 62 175 #define IRQ_MMP2_SM 63 176 177 #define IRQ_MMP2_MUX_BASE 64 178 179 /* secondary interrupt of INT #4 */ 180 #define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) 181 #define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) 182 #define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) 183 184 /* secondary interrupt of INT #5 */ 185 #define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) 186 #define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) 187 #define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) 188 189 /* secondary interrupt of INT #9 */ 190 #define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2) 191 #define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0) 192 #define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1) 193 #define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2) 194 195 /* secondary interrupt of INT #17 */ 196 #define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3) 197 #define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) 198 #define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) 199 #define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) 200 #define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) 201 #define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) 202 203 /* secondary interrupt of INT #35 */ 204 #define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) 205 #define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) 206 #define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) 207 #define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) 208 #define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) 209 #define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) 210 #define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) 211 #define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) 212 #define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) 213 #define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) 214 #define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) 215 #define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) 216 #define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) 217 #define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) 218 #define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) 219 220 /* secondary interrupt of INT #51 */ 221 #define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15) 222 #define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0) 223 #define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1) 224 225 /* secondary interrupt of INT #55 */ 226 #define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2) 227 #define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0) 228 #define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1) 229 230 #define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2) 231 232 #define IRQ_GPIO_START 128 233 #define MMP_NR_BUILTIN_GPIO 192 234 #define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio)) 235 236 #define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO) 237 #define MMP_NR_IRQS IRQ_BOARD_START 238 239 #endif /* __ASM_MACH_IRQS_H */ 240