1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved. 7 */ 8 #ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H 9 #define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H 10 11 #include <asm/sn/intr.h> 12 #include <asm/sn/pcibus_provider_defs.h> 13 14 /* Workarounds */ 15 #define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */ 16 17 #define BUSTYPE_MASK 0x1 18 19 /* Macros given a pcibus structure */ 20 #define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK) 21 #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \ 22 asic == PCIIO_ASIC_TYPE_TIOCP) 23 #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) 24 #define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP) 25 26 27 /* 28 * The different PCI Bridge types supported on the SGI Altix platforms 29 */ 30 #define PCIBR_BRIDGETYPE_UNKNOWN -1 31 #define PCIBR_BRIDGETYPE_PIC 2 32 #define PCIBR_BRIDGETYPE_TIOCP 3 33 34 /* 35 * Bridge 64bit Direct Map Attributes 36 */ 37 #define PCI64_ATTR_PREF (1ull << 59) 38 #define PCI64_ATTR_PREC (1ull << 58) 39 #define PCI64_ATTR_VIRTUAL (1ull << 57) 40 #define PCI64_ATTR_BAR (1ull << 56) 41 #define PCI64_ATTR_SWAP (1ull << 55) 42 #define PCI64_ATTR_VIRTUAL1 (1ull << 54) 43 44 #define PCI32_LOCAL_BASE 0 45 #define PCI32_MAPPED_BASE 0x40000000 46 #define PCI32_DIRECT_BASE 0x80000000 47 48 #define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \ 49 (u64)(x) >= PCI32_MAPPED_BASE) 50 #define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE) 51 52 53 /* 54 * Bridge PMU Address Transaltion Entry Attibutes 55 */ 56 #define PCI32_ATE_V (0x1 << 0) 57 #define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */ 58 #define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */ 59 #define PCI32_ATE_MSI (0x1 << 2) 60 #define PCI32_ATE_PREF (0x1 << 3) 61 #define PCI32_ATE_BAR (0x1 << 4) 62 #define PCI32_ATE_ADDR_SHFT 12 63 64 #define MINIMAL_ATES_REQUIRED(addr, size) \ 65 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1)) 66 67 #define MINIMAL_ATE_FLAG(addr, size) \ 68 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0) 69 70 /* bit 29 of the pci address is the SWAP bit */ 71 #define ATE_SWAPSHIFT 29 72 #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) 73 #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) 74 75 /* 76 * I/O page size 77 */ 78 #if PAGE_SIZE < 16384 79 #define IOPFNSHIFT 12 /* 4K per mapped page */ 80 #else 81 #define IOPFNSHIFT 14 /* 16K per mapped page */ 82 #endif 83 84 #define IOPGSIZE (1 << IOPFNSHIFT) 85 #define IOPG(x) ((x) >> IOPFNSHIFT) 86 #define IOPGOFF(x) ((x) & (IOPGSIZE-1)) 87 88 #define PCIBR_DEV_SWAP_DIR (1ull << 19) 89 #define PCIBR_CTRL_PAGE_SIZE (0x1 << 21) 90 91 /* 92 * PMU resources. 93 */ 94 struct ate_resource{ 95 u64 *ate; 96 u64 num_ate; 97 u64 lowest_free_index; 98 }; 99 100 struct pcibus_info { 101 struct pcibus_bussoft pbi_buscommon; /* common header */ 102 u32 pbi_moduleid; 103 short pbi_bridge_type; 104 short pbi_bridge_mode; 105 106 struct ate_resource pbi_int_ate_resource; 107 u64 pbi_int_ate_size; 108 109 u64 pbi_dir_xbase; 110 char pbi_hub_xid; 111 112 u64 pbi_devreg[8]; 113 114 u32 pbi_valid_devices; 115 u32 pbi_enabled_devices; 116 117 spinlock_t pbi_lock; 118 }; 119 120 extern int pcibr_init_provider(void); 121 extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *); 122 extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type); 123 extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type); 124 extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int); 125 126 /* 127 * prototypes for the bridge asic register access routines in pcibr_reg.c 128 */ 129 extern void pcireg_control_bit_clr(struct pcibus_info *, u64); 130 extern void pcireg_control_bit_set(struct pcibus_info *, u64); 131 extern u64 pcireg_tflush_get(struct pcibus_info *); 132 extern u64 pcireg_intr_status_get(struct pcibus_info *); 133 extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64); 134 extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64); 135 extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64); 136 extern void pcireg_force_intr_set(struct pcibus_info *, int); 137 extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int); 138 extern void pcireg_int_ate_set(struct pcibus_info *, int, u64); 139 extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int); 140 extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info); 141 extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info); 142 extern int pcibr_ate_alloc(struct pcibus_info *, int); 143 extern void pcibr_ate_free(struct pcibus_info *, int); 144 extern void ate_write(struct pcibus_info *, int, int, u64); 145 extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device, 146 void *resp, char **ssdt); 147 extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device, 148 int action, void *resp); 149 extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus); 150 #endif 151