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1 #ifndef __ASM_SH_PROCESSOR_H
2 #define __ASM_SH_PROCESSOR_H
3 
4 #include <asm/cpu-features.h>
5 #include <asm/segment.h>
6 #include <asm/cache.h>
7 
8 #ifndef __ASSEMBLY__
9 /*
10  *  CPU type and hardware bug flags. Kept separately for each CPU.
11  *
12  *  Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
13  *  in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
14  *  for parsing the subtype in get_cpu_subtype().
15  */
16 enum cpu_type {
17 	/* SH-2 types */
18 	CPU_SH7619,
19 
20 	/* SH-2A types */
21 	CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
22 	CPU_MXG,
23 
24 	/* SH-3 types */
25 	CPU_SH7705, CPU_SH7706, CPU_SH7707,
26 	CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
27 	CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
28 	CPU_SH7720, CPU_SH7721, CPU_SH7729,
29 
30 	/* SH-4 types */
31 	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
32 	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
33 
34 	/* SH-4A types */
35 	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
36 	CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SH7734, CPU_SHX3,
37 
38 	/* SH4AL-DSP types */
39 	CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
40 
41 	/* SH-5 types */
42         CPU_SH5_101, CPU_SH5_103,
43 
44 	/* Unknown subtype */
45 	CPU_SH_NONE
46 };
47 
48 enum cpu_family {
49 	CPU_FAMILY_SH2,
50 	CPU_FAMILY_SH2A,
51 	CPU_FAMILY_SH3,
52 	CPU_FAMILY_SH4,
53 	CPU_FAMILY_SH4A,
54 	CPU_FAMILY_SH4AL_DSP,
55 	CPU_FAMILY_SH5,
56 	CPU_FAMILY_UNKNOWN,
57 };
58 
59 /*
60  * TLB information structure
61  *
62  * Defined for both I and D tlb, per-processor.
63  */
64 struct tlb_info {
65 	unsigned long long next;
66 	unsigned long long first;
67 	unsigned long long last;
68 
69 	unsigned int entries;
70 	unsigned int step;
71 
72 	unsigned long flags;
73 };
74 
75 struct sh_cpuinfo {
76 	unsigned int type, family;
77 	int cut_major, cut_minor;
78 	unsigned long loops_per_jiffy;
79 	unsigned long asid_cache;
80 
81 	struct cache_info icache;	/* Primary I-cache */
82 	struct cache_info dcache;	/* Primary D-cache */
83 	struct cache_info scache;	/* Secondary cache */
84 
85 	/* TLB info */
86 	struct tlb_info itlb;
87 	struct tlb_info dtlb;
88 
89 	unsigned int phys_bits;
90 	unsigned long flags;
91 } __attribute__ ((aligned(L1_CACHE_BYTES)));
92 
93 extern struct sh_cpuinfo cpu_data[];
94 #define boot_cpu_data cpu_data[0]
95 #define current_cpu_data cpu_data[smp_processor_id()]
96 #define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
97 
98 #define cpu_sleep()	__asm__ __volatile__ ("sleep" : : : "memory")
99 #define cpu_relax()	barrier()
100 #define cpu_relax_lowlatency() cpu_relax()
101 
102 void default_idle(void);
103 void stop_this_cpu(void *);
104 
105 /* Forward decl */
106 struct seq_operations;
107 struct task_struct;
108 
109 extern struct pt_regs fake_swapper_regs;
110 
111 extern void cpu_init(void);
112 extern void cpu_probe(void);
113 
114 /* arch/sh/kernel/process.c */
115 extern unsigned int xstate_size;
116 extern void free_thread_xstate(struct task_struct *);
117 extern struct kmem_cache *task_xstate_cachep;
118 
119 /* arch/sh/mm/alignment.c */
120 extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
121 extern int set_unalign_ctl(struct task_struct *, unsigned int val);
122 
123 #define GET_UNALIGN_CTL(tsk, addr)	get_unalign_ctl((tsk), (addr))
124 #define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
125 
126 /* arch/sh/mm/init.c */
127 extern unsigned int mem_init_done;
128 
129 /* arch/sh/kernel/setup.c */
130 const char *get_cpu_subtype(struct sh_cpuinfo *c);
131 extern const struct seq_operations cpuinfo_op;
132 
133 /* thread_struct flags */
134 #define SH_THREAD_UAC_NOPRINT	(1 << 0)
135 #define SH_THREAD_UAC_SIGBUS	(1 << 1)
136 #define SH_THREAD_UAC_MASK	(SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
137 
138 /* processor boot mode configuration */
139 #define MODE_PIN0 (1 << 0)
140 #define MODE_PIN1 (1 << 1)
141 #define MODE_PIN2 (1 << 2)
142 #define MODE_PIN3 (1 << 3)
143 #define MODE_PIN4 (1 << 4)
144 #define MODE_PIN5 (1 << 5)
145 #define MODE_PIN6 (1 << 6)
146 #define MODE_PIN7 (1 << 7)
147 #define MODE_PIN8 (1 << 8)
148 #define MODE_PIN9 (1 << 9)
149 #define MODE_PIN10 (1 << 10)
150 #define MODE_PIN11 (1 << 11)
151 #define MODE_PIN12 (1 << 12)
152 #define MODE_PIN13 (1 << 13)
153 #define MODE_PIN14 (1 << 14)
154 #define MODE_PIN15 (1 << 15)
155 
156 int generic_mode_pins(void);
157 int test_mode_pin(int pin);
158 
159 #ifdef CONFIG_VSYSCALL
160 int vsyscall_init(void);
161 #else
162 #define vsyscall_init() do { } while (0)
163 #endif
164 
165 /*
166  * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
167  */
168 #ifdef CONFIG_CPU_SH2A
169 extern unsigned int instruction_size(unsigned int insn);
170 #elif defined(CONFIG_SUPERH32)
171 #define instruction_size(insn)	(2)
172 #else
173 #define instruction_size(insn)	(4)
174 #endif
175 
176 #endif /* __ASSEMBLY__ */
177 
178 #ifdef CONFIG_SUPERH32
179 # include <asm/processor_32.h>
180 #else
181 # include <asm/processor_64.h>
182 #endif
183 
184 #endif /* __ASM_SH_PROCESSOR_H */
185