1 #include <linux/perf_event.h>
2 #include <linux/types.h>
3
4 #include <asm/perf_event.h>
5 #include <asm/msr.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 enum {
11 LBR_FORMAT_32 = 0x00,
12 LBR_FORMAT_LIP = 0x01,
13 LBR_FORMAT_EIP = 0x02,
14 LBR_FORMAT_EIP_FLAGS = 0x03,
15 LBR_FORMAT_EIP_FLAGS2 = 0x04,
16 LBR_FORMAT_INFO = 0x05,
17 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_INFO,
18 };
19
20 static enum {
21 LBR_EIP_FLAGS = 1,
22 LBR_TSX = 2,
23 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
24 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
25 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
26 };
27
28 /*
29 * Intel LBR_SELECT bits
30 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
31 *
32 * Hardware branch filter (not available on all CPUs)
33 */
34 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
35 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
36 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
37 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
38 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
39 #define LBR_RETURN_BIT 5 /* do not capture near returns */
40 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
41 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
42 #define LBR_FAR_BIT 8 /* do not capture far branches */
43 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
44
45 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
46 #define LBR_USER (1 << LBR_USER_BIT)
47 #define LBR_JCC (1 << LBR_JCC_BIT)
48 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
49 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
50 #define LBR_RETURN (1 << LBR_RETURN_BIT)
51 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
52 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
53 #define LBR_FAR (1 << LBR_FAR_BIT)
54 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
55
56 #define LBR_PLM (LBR_KERNEL | LBR_USER)
57
58 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
59 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
60 #define LBR_IGN 0 /* ignored */
61
62 #define LBR_ANY \
63 (LBR_JCC |\
64 LBR_REL_CALL |\
65 LBR_IND_CALL |\
66 LBR_RETURN |\
67 LBR_REL_JMP |\
68 LBR_IND_JMP |\
69 LBR_FAR)
70
71 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
72 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
73 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
74
75 /*
76 * x86control flow change classification
77 * x86control flow changes include branches, interrupts, traps, faults
78 */
79 enum {
80 X86_BR_NONE = 0, /* unknown */
81
82 X86_BR_USER = 1 << 0, /* branch target is user */
83 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
84
85 X86_BR_CALL = 1 << 2, /* call */
86 X86_BR_RET = 1 << 3, /* return */
87 X86_BR_SYSCALL = 1 << 4, /* syscall */
88 X86_BR_SYSRET = 1 << 5, /* syscall return */
89 X86_BR_INT = 1 << 6, /* sw interrupt */
90 X86_BR_IRET = 1 << 7, /* return from interrupt */
91 X86_BR_JCC = 1 << 8, /* conditional */
92 X86_BR_JMP = 1 << 9, /* jump */
93 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
94 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
95 X86_BR_ABORT = 1 << 12,/* transaction abort */
96 X86_BR_IN_TX = 1 << 13,/* in transaction */
97 X86_BR_NO_TX = 1 << 14,/* not in transaction */
98 X86_BR_ZERO_CALL = 1 << 15,/* zero length call */
99 X86_BR_CALL_STACK = 1 << 16,/* call stack */
100 X86_BR_IND_JMP = 1 << 17,/* indirect jump */
101 };
102
103 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
104 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
105
106 #define X86_BR_ANY \
107 (X86_BR_CALL |\
108 X86_BR_RET |\
109 X86_BR_SYSCALL |\
110 X86_BR_SYSRET |\
111 X86_BR_INT |\
112 X86_BR_IRET |\
113 X86_BR_JCC |\
114 X86_BR_JMP |\
115 X86_BR_IRQ |\
116 X86_BR_ABORT |\
117 X86_BR_IND_CALL |\
118 X86_BR_IND_JMP |\
119 X86_BR_ZERO_CALL)
120
121 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
122
123 #define X86_BR_ANY_CALL \
124 (X86_BR_CALL |\
125 X86_BR_IND_CALL |\
126 X86_BR_ZERO_CALL |\
127 X86_BR_SYSCALL |\
128 X86_BR_IRQ |\
129 X86_BR_INT)
130
131 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
132
133 /*
134 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
135 * otherwise it becomes near impossible to get a reliable stack.
136 */
137
__intel_pmu_lbr_enable(bool pmi)138 static void __intel_pmu_lbr_enable(bool pmi)
139 {
140 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
141 u64 debugctl, lbr_select = 0, orig_debugctl;
142
143 /*
144 * No need to unfreeze manually, as v4 can do that as part
145 * of the GLOBAL_STATUS ack.
146 */
147 if (pmi && x86_pmu.version >= 4)
148 return;
149
150 /*
151 * No need to reprogram LBR_SELECT in a PMI, as it
152 * did not change.
153 */
154 if (cpuc->lbr_sel)
155 lbr_select = cpuc->lbr_sel->config;
156 if (!pmi && cpuc->lbr_sel)
157 wrmsrl(MSR_LBR_SELECT, lbr_select);
158
159 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
160 orig_debugctl = debugctl;
161 debugctl |= DEBUGCTLMSR_LBR;
162 /*
163 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
164 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
165 * may cause superfluous increase/decrease of LBR_TOS.
166 */
167 if (!(lbr_select & LBR_CALL_STACK))
168 debugctl |= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI;
169 if (orig_debugctl != debugctl)
170 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
171 }
172
__intel_pmu_lbr_disable(void)173 static void __intel_pmu_lbr_disable(void)
174 {
175 u64 debugctl;
176
177 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
178 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
179 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
180 }
181
intel_pmu_lbr_reset_32(void)182 static void intel_pmu_lbr_reset_32(void)
183 {
184 int i;
185
186 for (i = 0; i < x86_pmu.lbr_nr; i++)
187 wrmsrl(x86_pmu.lbr_from + i, 0);
188 }
189
intel_pmu_lbr_reset_64(void)190 static void intel_pmu_lbr_reset_64(void)
191 {
192 int i;
193
194 for (i = 0; i < x86_pmu.lbr_nr; i++) {
195 wrmsrl(x86_pmu.lbr_from + i, 0);
196 wrmsrl(x86_pmu.lbr_to + i, 0);
197 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
198 wrmsrl(MSR_LBR_INFO_0 + i, 0);
199 }
200 }
201
intel_pmu_lbr_reset(void)202 void intel_pmu_lbr_reset(void)
203 {
204 if (!x86_pmu.lbr_nr)
205 return;
206
207 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
208 intel_pmu_lbr_reset_32();
209 else
210 intel_pmu_lbr_reset_64();
211 }
212
213 /*
214 * TOS = most recently recorded branch
215 */
intel_pmu_lbr_tos(void)216 static inline u64 intel_pmu_lbr_tos(void)
217 {
218 u64 tos;
219
220 rdmsrl(x86_pmu.lbr_tos, tos);
221 return tos;
222 }
223
224 enum {
225 LBR_NONE,
226 LBR_VALID,
227 };
228
__intel_pmu_lbr_restore(struct x86_perf_task_context * task_ctx)229 static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
230 {
231 int i;
232 unsigned lbr_idx, mask;
233 u64 tos;
234
235 if (task_ctx->lbr_callstack_users == 0 ||
236 task_ctx->lbr_stack_state == LBR_NONE) {
237 intel_pmu_lbr_reset();
238 return;
239 }
240
241 mask = x86_pmu.lbr_nr - 1;
242 tos = task_ctx->tos;
243 for (i = 0; i < tos; i++) {
244 lbr_idx = (tos - i) & mask;
245 wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]);
246 wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]);
247 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
248 wrmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
249 }
250 wrmsrl(x86_pmu.lbr_tos, tos);
251 task_ctx->lbr_stack_state = LBR_NONE;
252 }
253
__intel_pmu_lbr_save(struct x86_perf_task_context * task_ctx)254 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
255 {
256 int i;
257 unsigned lbr_idx, mask;
258 u64 tos;
259
260 if (task_ctx->lbr_callstack_users == 0) {
261 task_ctx->lbr_stack_state = LBR_NONE;
262 return;
263 }
264
265 mask = x86_pmu.lbr_nr - 1;
266 tos = intel_pmu_lbr_tos();
267 for (i = 0; i < tos; i++) {
268 lbr_idx = (tos - i) & mask;
269 rdmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]);
270 rdmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]);
271 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
272 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
273 }
274 task_ctx->tos = tos;
275 task_ctx->lbr_stack_state = LBR_VALID;
276 }
277
intel_pmu_lbr_sched_task(struct perf_event_context * ctx,bool sched_in)278 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in)
279 {
280 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
281 struct x86_perf_task_context *task_ctx;
282
283 /*
284 * If LBR callstack feature is enabled and the stack was saved when
285 * the task was scheduled out, restore the stack. Otherwise flush
286 * the LBR stack.
287 */
288 task_ctx = ctx ? ctx->task_ctx_data : NULL;
289 if (task_ctx) {
290 if (sched_in) {
291 __intel_pmu_lbr_restore(task_ctx);
292 cpuc->lbr_context = ctx;
293 } else {
294 __intel_pmu_lbr_save(task_ctx);
295 }
296 return;
297 }
298
299 /*
300 * When sampling the branck stack in system-wide, it may be
301 * necessary to flush the stack on context switch. This happens
302 * when the branch stack does not tag its entries with the pid
303 * of the current task. Otherwise it becomes impossible to
304 * associate a branch entry with a task. This ambiguity is more
305 * likely to appear when the branch stack supports priv level
306 * filtering and the user sets it to monitor only at the user
307 * level (which could be a useful measurement in system-wide
308 * mode). In that case, the risk is high of having a branch
309 * stack with branch from multiple tasks.
310 */
311 if (sched_in) {
312 intel_pmu_lbr_reset();
313 cpuc->lbr_context = ctx;
314 }
315 }
316
branch_user_callstack(unsigned br_sel)317 static inline bool branch_user_callstack(unsigned br_sel)
318 {
319 return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK);
320 }
321
intel_pmu_lbr_enable(struct perf_event * event)322 void intel_pmu_lbr_enable(struct perf_event *event)
323 {
324 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
325 struct x86_perf_task_context *task_ctx;
326
327 if (!x86_pmu.lbr_nr)
328 return;
329
330 /*
331 * Reset the LBR stack if we changed task context to
332 * avoid data leaks.
333 */
334 if (event->ctx->task && cpuc->lbr_context != event->ctx) {
335 intel_pmu_lbr_reset();
336 cpuc->lbr_context = event->ctx;
337 }
338 cpuc->br_sel = event->hw.branch_reg.reg;
339
340 if (branch_user_callstack(cpuc->br_sel) && event->ctx &&
341 event->ctx->task_ctx_data) {
342 task_ctx = event->ctx->task_ctx_data;
343 task_ctx->lbr_callstack_users++;
344 }
345
346 cpuc->lbr_users++;
347 perf_sched_cb_inc(event->ctx->pmu);
348 }
349
intel_pmu_lbr_disable(struct perf_event * event)350 void intel_pmu_lbr_disable(struct perf_event *event)
351 {
352 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
353 struct x86_perf_task_context *task_ctx;
354
355 if (!x86_pmu.lbr_nr)
356 return;
357
358 if (branch_user_callstack(cpuc->br_sel) && event->ctx &&
359 event->ctx->task_ctx_data) {
360 task_ctx = event->ctx->task_ctx_data;
361 task_ctx->lbr_callstack_users--;
362 }
363
364 cpuc->lbr_users--;
365 WARN_ON_ONCE(cpuc->lbr_users < 0);
366 perf_sched_cb_dec(event->ctx->pmu);
367
368 if (cpuc->enabled && !cpuc->lbr_users) {
369 __intel_pmu_lbr_disable();
370 /* avoid stale pointer */
371 cpuc->lbr_context = NULL;
372 }
373 }
374
intel_pmu_lbr_enable_all(bool pmi)375 void intel_pmu_lbr_enable_all(bool pmi)
376 {
377 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
378
379 if (cpuc->lbr_users)
380 __intel_pmu_lbr_enable(pmi);
381 }
382
intel_pmu_lbr_disable_all(void)383 void intel_pmu_lbr_disable_all(void)
384 {
385 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
386
387 if (cpuc->lbr_users)
388 __intel_pmu_lbr_disable();
389 }
390
intel_pmu_lbr_read_32(struct cpu_hw_events * cpuc)391 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
392 {
393 unsigned long mask = x86_pmu.lbr_nr - 1;
394 u64 tos = intel_pmu_lbr_tos();
395 int i;
396
397 for (i = 0; i < x86_pmu.lbr_nr; i++) {
398 unsigned long lbr_idx = (tos - i) & mask;
399 union {
400 struct {
401 u32 from;
402 u32 to;
403 };
404 u64 lbr;
405 } msr_lastbranch;
406
407 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
408
409 cpuc->lbr_entries[i].from = msr_lastbranch.from;
410 cpuc->lbr_entries[i].to = msr_lastbranch.to;
411 cpuc->lbr_entries[i].mispred = 0;
412 cpuc->lbr_entries[i].predicted = 0;
413 cpuc->lbr_entries[i].in_tx = 0;
414 cpuc->lbr_entries[i].abort = 0;
415 cpuc->lbr_entries[i].cycles = 0;
416 cpuc->lbr_entries[i].reserved = 0;
417 }
418 cpuc->lbr_stack.nr = i;
419 }
420
421 /*
422 * Due to lack of segmentation in Linux the effective address (offset)
423 * is the same as the linear address, allowing us to merge the LIP and EIP
424 * LBR formats.
425 */
intel_pmu_lbr_read_64(struct cpu_hw_events * cpuc)426 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
427 {
428 unsigned long mask = x86_pmu.lbr_nr - 1;
429 int lbr_format = x86_pmu.intel_cap.lbr_format;
430 u64 tos = intel_pmu_lbr_tos();
431 int i;
432 int out = 0;
433 int num = x86_pmu.lbr_nr;
434
435 if (cpuc->lbr_sel) {
436 if (cpuc->lbr_sel->config & LBR_CALL_STACK)
437 num = tos;
438 }
439
440 for (i = 0; i < num; i++) {
441 unsigned long lbr_idx = (tos - i) & mask;
442 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
443 int skip = 0;
444 u16 cycles = 0;
445 int lbr_flags = lbr_desc[lbr_format];
446
447 rdmsrl(x86_pmu.lbr_from + lbr_idx, from);
448 rdmsrl(x86_pmu.lbr_to + lbr_idx, to);
449
450 if (lbr_format == LBR_FORMAT_INFO) {
451 u64 info;
452
453 rdmsrl(MSR_LBR_INFO_0 + lbr_idx, info);
454 mis = !!(info & LBR_INFO_MISPRED);
455 pred = !mis;
456 in_tx = !!(info & LBR_INFO_IN_TX);
457 abort = !!(info & LBR_INFO_ABORT);
458 cycles = (info & LBR_INFO_CYCLES);
459 }
460 if (lbr_flags & LBR_EIP_FLAGS) {
461 mis = !!(from & LBR_FROM_FLAG_MISPRED);
462 pred = !mis;
463 skip = 1;
464 }
465 if (lbr_flags & LBR_TSX) {
466 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
467 abort = !!(from & LBR_FROM_FLAG_ABORT);
468 skip = 3;
469 }
470 from = (u64)((((s64)from) << skip) >> skip);
471
472 /*
473 * Some CPUs report duplicated abort records,
474 * with the second entry not having an abort bit set.
475 * Skip them here. This loop runs backwards,
476 * so we need to undo the previous record.
477 * If the abort just happened outside the window
478 * the extra entry cannot be removed.
479 */
480 if (abort && x86_pmu.lbr_double_abort && out > 0)
481 out--;
482
483 cpuc->lbr_entries[out].from = from;
484 cpuc->lbr_entries[out].to = to;
485 cpuc->lbr_entries[out].mispred = mis;
486 cpuc->lbr_entries[out].predicted = pred;
487 cpuc->lbr_entries[out].in_tx = in_tx;
488 cpuc->lbr_entries[out].abort = abort;
489 cpuc->lbr_entries[out].cycles = cycles;
490 cpuc->lbr_entries[out].reserved = 0;
491 out++;
492 }
493 cpuc->lbr_stack.nr = out;
494 }
495
intel_pmu_lbr_read(void)496 void intel_pmu_lbr_read(void)
497 {
498 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
499
500 if (!cpuc->lbr_users)
501 return;
502
503 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
504 intel_pmu_lbr_read_32(cpuc);
505 else
506 intel_pmu_lbr_read_64(cpuc);
507
508 intel_pmu_lbr_filter(cpuc);
509 }
510
511 /*
512 * SW filter is used:
513 * - in case there is no HW filter
514 * - in case the HW filter has errata or limitations
515 */
intel_pmu_setup_sw_lbr_filter(struct perf_event * event)516 static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
517 {
518 u64 br_type = event->attr.branch_sample_type;
519 int mask = 0;
520
521 if (br_type & PERF_SAMPLE_BRANCH_USER)
522 mask |= X86_BR_USER;
523
524 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
525 mask |= X86_BR_KERNEL;
526
527 /* we ignore BRANCH_HV here */
528
529 if (br_type & PERF_SAMPLE_BRANCH_ANY)
530 mask |= X86_BR_ANY;
531
532 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
533 mask |= X86_BR_ANY_CALL;
534
535 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
536 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
537
538 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
539 mask |= X86_BR_IND_CALL;
540
541 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
542 mask |= X86_BR_ABORT;
543
544 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
545 mask |= X86_BR_IN_TX;
546
547 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
548 mask |= X86_BR_NO_TX;
549
550 if (br_type & PERF_SAMPLE_BRANCH_COND)
551 mask |= X86_BR_JCC;
552
553 if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) {
554 if (!x86_pmu_has_lbr_callstack())
555 return -EOPNOTSUPP;
556 if (mask & ~(X86_BR_USER | X86_BR_KERNEL))
557 return -EINVAL;
558 mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET |
559 X86_BR_CALL_STACK;
560 }
561
562 if (br_type & PERF_SAMPLE_BRANCH_IND_JUMP)
563 mask |= X86_BR_IND_JMP;
564
565 if (br_type & PERF_SAMPLE_BRANCH_CALL)
566 mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
567 /*
568 * stash actual user request into reg, it may
569 * be used by fixup code for some CPU
570 */
571 event->hw.branch_reg.reg = mask;
572 return 0;
573 }
574
575 /*
576 * setup the HW LBR filter
577 * Used only when available, may not be enough to disambiguate
578 * all branches, may need the help of the SW filter
579 */
intel_pmu_setup_hw_lbr_filter(struct perf_event * event)580 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
581 {
582 struct hw_perf_event_extra *reg;
583 u64 br_type = event->attr.branch_sample_type;
584 u64 mask = 0, v;
585 int i;
586
587 for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
588 if (!(br_type & (1ULL << i)))
589 continue;
590
591 v = x86_pmu.lbr_sel_map[i];
592 if (v == LBR_NOT_SUPP)
593 return -EOPNOTSUPP;
594
595 if (v != LBR_IGN)
596 mask |= v;
597 }
598 reg = &event->hw.branch_reg;
599 reg->idx = EXTRA_REG_LBR;
600
601 /*
602 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
603 * in suppress mode. So LBR_SELECT should be set to
604 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
605 */
606 reg->config = mask ^ x86_pmu.lbr_sel_mask;
607
608 return 0;
609 }
610
intel_pmu_setup_lbr_filter(struct perf_event * event)611 int intel_pmu_setup_lbr_filter(struct perf_event *event)
612 {
613 int ret = 0;
614
615 /*
616 * no LBR on this PMU
617 */
618 if (!x86_pmu.lbr_nr)
619 return -EOPNOTSUPP;
620
621 /*
622 * setup SW LBR filter
623 */
624 ret = intel_pmu_setup_sw_lbr_filter(event);
625 if (ret)
626 return ret;
627
628 /*
629 * setup HW LBR filter, if any
630 */
631 if (x86_pmu.lbr_sel_map)
632 ret = intel_pmu_setup_hw_lbr_filter(event);
633
634 return ret;
635 }
636
637 /*
638 * return the type of control flow change at address "from"
639 * intruction is not necessarily a branch (in case of interrupt).
640 *
641 * The branch type returned also includes the priv level of the
642 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
643 *
644 * If a branch type is unknown OR the instruction cannot be
645 * decoded (e.g., text page not present), then X86_BR_NONE is
646 * returned.
647 */
branch_type(unsigned long from,unsigned long to,int abort)648 static int branch_type(unsigned long from, unsigned long to, int abort)
649 {
650 struct insn insn;
651 void *addr;
652 int bytes_read, bytes_left;
653 int ret = X86_BR_NONE;
654 int ext, to_plm, from_plm;
655 u8 buf[MAX_INSN_SIZE];
656 int is64 = 0;
657
658 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
659 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
660
661 /*
662 * maybe zero if lbr did not fill up after a reset by the time
663 * we get a PMU interrupt
664 */
665 if (from == 0 || to == 0)
666 return X86_BR_NONE;
667
668 if (abort)
669 return X86_BR_ABORT | to_plm;
670
671 if (from_plm == X86_BR_USER) {
672 /*
673 * can happen if measuring at the user level only
674 * and we interrupt in a kernel thread, e.g., idle.
675 */
676 if (!current->mm)
677 return X86_BR_NONE;
678
679 /* may fail if text not present */
680 bytes_left = copy_from_user_nmi(buf, (void __user *)from,
681 MAX_INSN_SIZE);
682 bytes_read = MAX_INSN_SIZE - bytes_left;
683 if (!bytes_read)
684 return X86_BR_NONE;
685
686 addr = buf;
687 } else {
688 /*
689 * The LBR logs any address in the IP, even if the IP just
690 * faulted. This means userspace can control the from address.
691 * Ensure we don't blindy read any address by validating it is
692 * a known text address.
693 */
694 if (kernel_text_address(from)) {
695 addr = (void *)from;
696 /*
697 * Assume we can get the maximum possible size
698 * when grabbing kernel data. This is not
699 * _strictly_ true since we could possibly be
700 * executing up next to a memory hole, but
701 * it is very unlikely to be a problem.
702 */
703 bytes_read = MAX_INSN_SIZE;
704 } else {
705 return X86_BR_NONE;
706 }
707 }
708
709 /*
710 * decoder needs to know the ABI especially
711 * on 64-bit systems running 32-bit apps
712 */
713 #ifdef CONFIG_X86_64
714 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
715 #endif
716 insn_init(&insn, addr, bytes_read, is64);
717 insn_get_opcode(&insn);
718 if (!insn.opcode.got)
719 return X86_BR_ABORT;
720
721 switch (insn.opcode.bytes[0]) {
722 case 0xf:
723 switch (insn.opcode.bytes[1]) {
724 case 0x05: /* syscall */
725 case 0x34: /* sysenter */
726 ret = X86_BR_SYSCALL;
727 break;
728 case 0x07: /* sysret */
729 case 0x35: /* sysexit */
730 ret = X86_BR_SYSRET;
731 break;
732 case 0x80 ... 0x8f: /* conditional */
733 ret = X86_BR_JCC;
734 break;
735 default:
736 ret = X86_BR_NONE;
737 }
738 break;
739 case 0x70 ... 0x7f: /* conditional */
740 ret = X86_BR_JCC;
741 break;
742 case 0xc2: /* near ret */
743 case 0xc3: /* near ret */
744 case 0xca: /* far ret */
745 case 0xcb: /* far ret */
746 ret = X86_BR_RET;
747 break;
748 case 0xcf: /* iret */
749 ret = X86_BR_IRET;
750 break;
751 case 0xcc ... 0xce: /* int */
752 ret = X86_BR_INT;
753 break;
754 case 0xe8: /* call near rel */
755 insn_get_immediate(&insn);
756 if (insn.immediate1.value == 0) {
757 /* zero length call */
758 ret = X86_BR_ZERO_CALL;
759 break;
760 }
761 case 0x9a: /* call far absolute */
762 ret = X86_BR_CALL;
763 break;
764 case 0xe0 ... 0xe3: /* loop jmp */
765 ret = X86_BR_JCC;
766 break;
767 case 0xe9 ... 0xeb: /* jmp */
768 ret = X86_BR_JMP;
769 break;
770 case 0xff: /* call near absolute, call far absolute ind */
771 insn_get_modrm(&insn);
772 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
773 switch (ext) {
774 case 2: /* near ind call */
775 case 3: /* far ind call */
776 ret = X86_BR_IND_CALL;
777 break;
778 case 4:
779 case 5:
780 ret = X86_BR_IND_JMP;
781 break;
782 }
783 break;
784 default:
785 ret = X86_BR_NONE;
786 }
787 /*
788 * interrupts, traps, faults (and thus ring transition) may
789 * occur on any instructions. Thus, to classify them correctly,
790 * we need to first look at the from and to priv levels. If they
791 * are different and to is in the kernel, then it indicates
792 * a ring transition. If the from instruction is not a ring
793 * transition instr (syscall, systenter, int), then it means
794 * it was a irq, trap or fault.
795 *
796 * we have no way of detecting kernel to kernel faults.
797 */
798 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
799 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
800 ret = X86_BR_IRQ;
801
802 /*
803 * branch priv level determined by target as
804 * is done by HW when LBR_SELECT is implemented
805 */
806 if (ret != X86_BR_NONE)
807 ret |= to_plm;
808
809 return ret;
810 }
811
812 /*
813 * implement actual branch filter based on user demand.
814 * Hardware may not exactly satisfy that request, thus
815 * we need to inspect opcodes. Mismatched branches are
816 * discarded. Therefore, the number of branches returned
817 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
818 */
819 static void
intel_pmu_lbr_filter(struct cpu_hw_events * cpuc)820 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
821 {
822 u64 from, to;
823 int br_sel = cpuc->br_sel;
824 int i, j, type;
825 bool compress = false;
826
827 /* if sampling all branches, then nothing to filter */
828 if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
829 return;
830
831 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
832
833 from = cpuc->lbr_entries[i].from;
834 to = cpuc->lbr_entries[i].to;
835
836 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
837 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
838 if (cpuc->lbr_entries[i].in_tx)
839 type |= X86_BR_IN_TX;
840 else
841 type |= X86_BR_NO_TX;
842 }
843
844 /* if type does not correspond, then discard */
845 if (type == X86_BR_NONE || (br_sel & type) != type) {
846 cpuc->lbr_entries[i].from = 0;
847 compress = true;
848 }
849 }
850
851 if (!compress)
852 return;
853
854 /* remove all entries with from=0 */
855 for (i = 0; i < cpuc->lbr_stack.nr; ) {
856 if (!cpuc->lbr_entries[i].from) {
857 j = i;
858 while (++j < cpuc->lbr_stack.nr)
859 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
860 cpuc->lbr_stack.nr--;
861 if (!cpuc->lbr_entries[i].from)
862 continue;
863 }
864 i++;
865 }
866 }
867
868 /*
869 * Map interface branch filters onto LBR filters
870 */
871 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
872 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
873 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
874 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
875 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
876 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP
877 | LBR_IND_JMP | LBR_FAR,
878 /*
879 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
880 */
881 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] =
882 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
883 /*
884 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
885 */
886 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP,
887 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
888 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
889 };
890
891 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
892 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
893 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
894 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
895 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
896 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
897 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
898 | LBR_FAR,
899 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
900 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
901 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
902 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
903 };
904
905 static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
906 [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
907 [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
908 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
909 [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN,
910 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR,
911 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
912 | LBR_FAR,
913 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL,
914 [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
915 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL
916 | LBR_RETURN | LBR_CALL_STACK,
917 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT] = LBR_IND_JMP,
918 [PERF_SAMPLE_BRANCH_CALL_SHIFT] = LBR_REL_CALL,
919 };
920
921 /* core */
intel_pmu_lbr_init_core(void)922 void __init intel_pmu_lbr_init_core(void)
923 {
924 x86_pmu.lbr_nr = 4;
925 x86_pmu.lbr_tos = MSR_LBR_TOS;
926 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
927 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
928
929 /*
930 * SW branch filter usage:
931 * - compensate for lack of HW filter
932 */
933 pr_cont("4-deep LBR, ");
934 }
935
936 /* nehalem/westmere */
intel_pmu_lbr_init_nhm(void)937 void __init intel_pmu_lbr_init_nhm(void)
938 {
939 x86_pmu.lbr_nr = 16;
940 x86_pmu.lbr_tos = MSR_LBR_TOS;
941 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
942 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
943
944 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
945 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
946
947 /*
948 * SW branch filter usage:
949 * - workaround LBR_SEL errata (see above)
950 * - support syscall, sysret capture.
951 * That requires LBR_FAR but that means far
952 * jmp need to be filtered out
953 */
954 pr_cont("16-deep LBR, ");
955 }
956
957 /* sandy bridge */
intel_pmu_lbr_init_snb(void)958 void __init intel_pmu_lbr_init_snb(void)
959 {
960 x86_pmu.lbr_nr = 16;
961 x86_pmu.lbr_tos = MSR_LBR_TOS;
962 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
963 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
964
965 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
966 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
967
968 /*
969 * SW branch filter usage:
970 * - support syscall, sysret capture.
971 * That requires LBR_FAR but that means far
972 * jmp need to be filtered out
973 */
974 pr_cont("16-deep LBR, ");
975 }
976
977 /* haswell */
intel_pmu_lbr_init_hsw(void)978 void intel_pmu_lbr_init_hsw(void)
979 {
980 x86_pmu.lbr_nr = 16;
981 x86_pmu.lbr_tos = MSR_LBR_TOS;
982 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
983 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
984
985 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
986 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
987
988 pr_cont("16-deep LBR, ");
989 }
990
991 /* skylake */
intel_pmu_lbr_init_skl(void)992 __init void intel_pmu_lbr_init_skl(void)
993 {
994 x86_pmu.lbr_nr = 32;
995 x86_pmu.lbr_tos = MSR_LBR_TOS;
996 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
997 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
998
999 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
1000 x86_pmu.lbr_sel_map = hsw_lbr_sel_map;
1001
1002 /*
1003 * SW branch filter usage:
1004 * - support syscall, sysret capture.
1005 * That requires LBR_FAR but that means far
1006 * jmp need to be filtered out
1007 */
1008 pr_cont("32-deep LBR, ");
1009 }
1010
1011 /* atom */
intel_pmu_lbr_init_atom(void)1012 void __init intel_pmu_lbr_init_atom(void)
1013 {
1014 /*
1015 * only models starting at stepping 10 seems
1016 * to have an operational LBR which can freeze
1017 * on PMU interrupt
1018 */
1019 if (boot_cpu_data.x86_model == 28
1020 && boot_cpu_data.x86_stepping < 10) {
1021 pr_cont("LBR disabled due to erratum");
1022 return;
1023 }
1024
1025 x86_pmu.lbr_nr = 8;
1026 x86_pmu.lbr_tos = MSR_LBR_TOS;
1027 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
1028 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
1029
1030 /*
1031 * SW branch filter usage:
1032 * - compensate for lack of HW filter
1033 */
1034 pr_cont("8-deep LBR, ");
1035 }
1036