1 /* 2 * drxd_firm.h 3 * 4 * Copyright (C) 2006-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 20 * 02110-1301, USA 21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html 22 */ 23 24 #ifndef _DRXD_FIRM_H_ 25 #define _DRXD_FIRM_H_ 26 27 #include <linux/types.h> 28 #include "drxd_map_firm.h" 29 30 #define VERSION_MAJOR 1 31 #define VERSION_MINOR 4 32 #define VERSION_PATCH 23 33 34 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A 35 36 #define DRXD_MAX_RETRIES (1000) 37 #define HI_I2C_DELAY 84 38 #define HI_I2C_BRIDGE_DELAY 750 39 40 #define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ 41 #define EQ_TD_TPS_PWR_QPSK 0x016a 42 #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 43 #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 44 #define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E 45 #define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE 46 #define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F 47 #define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F 48 #define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8 49 #define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D 50 51 #define DRXD_DEF_AG_PWD_CONSUMER 0x000E 52 #define DRXD_DEF_AG_PWD_PRO 0x0000 53 #define DRXD_DEF_AG_AGC_SIO 0x0000 54 55 #define DRXD_FE_CTRL_MAX 1023 56 57 #define DRXD_OSCDEV_DO_SCAN (16) 58 59 #define DRXD_OSCDEV_DONT_SCAN (0) 60 61 #define DRXD_OSCDEV_STEP (275) 62 63 #define DRXD_SCAN_TIMEOUT (650) 64 65 #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) 66 #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) 67 #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) 68 69 #define IRLEN_COARSE_8K (10) 70 #define IRLEN_FINE_8K (10) 71 #define IRLEN_COARSE_2K (7) 72 #define IRLEN_FINE_2K (9) 73 #define DIFF_INVALID (511) 74 #define DIFF_TARGET (4) 75 #define DIFF_MARGIN (1) 76 77 extern u8 DRXD_InitAtomicRead[]; 78 extern u8 DRXD_HiI2cPatch_1[]; 79 extern u8 DRXD_HiI2cPatch_3[]; 80 81 extern u8 DRXD_InitSC[]; 82 83 extern u8 DRXD_ResetCEFR[]; 84 extern u8 DRXD_InitFEA2_1[]; 85 extern u8 DRXD_InitFEA2_2[]; 86 extern u8 DRXD_InitCPA2[]; 87 extern u8 DRXD_InitCEA2[]; 88 extern u8 DRXD_InitEQA2[]; 89 extern u8 DRXD_InitECA2[]; 90 extern u8 DRXD_ResetECA2[]; 91 extern u8 DRXD_ResetECRAM[]; 92 93 extern u8 DRXD_A2_microcode[]; 94 extern u32 DRXD_A2_microcode_length; 95 96 extern u8 DRXD_InitFEB1_1[]; 97 extern u8 DRXD_InitFEB1_2[]; 98 extern u8 DRXD_InitCPB1[]; 99 extern u8 DRXD_InitCEB1[]; 100 extern u8 DRXD_InitEQB1[]; 101 extern u8 DRXD_InitECB1[]; 102 103 extern u8 DRXD_InitDiversityFront[]; 104 extern u8 DRXD_InitDiversityEnd[]; 105 extern u8 DRXD_DisableDiversity[]; 106 extern u8 DRXD_StartDiversityFront[]; 107 extern u8 DRXD_StartDiversityEnd[]; 108 109 extern u8 DRXD_DiversityDelay8MHZ[]; 110 extern u8 DRXD_DiversityDelay6MHZ[]; 111 112 extern u8 DRXD_B1_microcode[]; 113 extern u32 DRXD_B1_microcode_length; 114 115 #endif 116