1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9002_phy.h"
20
ath9k_hw_4k_get_eeprom_ver(struct ath_hw * ah)21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
22 {
23 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
24 }
25
ath9k_hw_4k_get_eeprom_rev(struct ath_hw * ah)26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
27 {
28 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
29 }
30
31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
32
__ath9k_hw_4k_fill_eeprom(struct ath_hw * ah)33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
34 {
35 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
36 int addr, eep_start_loc = 64;
37
38 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
39 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data))
40 return false;
41 eep_data++;
42 }
43
44 return true;
45 }
46
__ath9k_hw_usb_4k_fill_eeprom(struct ath_hw * ah)47 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
48 {
49 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
50
51 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
52
53 return true;
54 }
55
ath9k_hw_4k_fill_eeprom(struct ath_hw * ah)56 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
57 {
58 struct ath_common *common = ath9k_hw_common(ah);
59
60 if (!ath9k_hw_use_flash(ah)) {
61 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
62 }
63
64 if (common->bus_ops->ath_bus_type == ATH_USB)
65 return __ath9k_hw_usb_4k_fill_eeprom(ah);
66 else
67 return __ath9k_hw_4k_fill_eeprom(ah);
68 }
69
70 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
ath9k_dump_4k_modal_eeprom(char * buf,u32 len,u32 size,struct modal_eep_4k_header * modal_hdr)71 static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
72 struct modal_eep_4k_header *modal_hdr)
73 {
74 PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
75 PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
76 PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
77 PR_EEP("Switch Settle", modal_hdr->switchSettling);
78 PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
79 PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
80 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
81 PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
82 PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
83 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
84 PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
85 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
86 PR_EEP("CCA Threshold)", modal_hdr->thresh62);
87 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
88 PR_EEP("xpdGain", modal_hdr->xpdGain);
89 PR_EEP("External PD", modal_hdr->xpd);
90 PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
91 PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
92 PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
93 PR_EEP("O/D Bias Version", modal_hdr->version);
94 PR_EEP("CCK OutputBias", modal_hdr->ob_0);
95 PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
96 PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
97 PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
98 PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
99 PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
100 PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
101 PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
102 PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
103 PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
104 PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
105 PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
106 PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
107 PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
108 PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
109 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
110 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
111 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
112 PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
113 PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
114 PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
115 PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
116 PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
117 PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
118 PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
119 PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
120 PR_EEP("TX Diversity", modal_hdr->tx_diversity);
121
122 return len;
123 }
124
ath9k_hw_4k_dump_eeprom(struct ath_hw * ah,bool dump_base_hdr,u8 * buf,u32 len,u32 size)125 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
126 u8 *buf, u32 len, u32 size)
127 {
128 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
129 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
130
131 if (!dump_base_hdr) {
132 len += scnprintf(buf + len, size - len,
133 "%20s :\n", "2GHz modal Header");
134 len = ath9k_dump_4k_modal_eeprom(buf, len, size,
135 &eep->modalHeader);
136 goto out;
137 }
138
139 PR_EEP("Major Version", pBase->version >> 12);
140 PR_EEP("Minor Version", pBase->version & 0xFFF);
141 PR_EEP("Checksum", pBase->checksum);
142 PR_EEP("Length", pBase->length);
143 PR_EEP("RegDomain1", pBase->regDmn[0]);
144 PR_EEP("RegDomain2", pBase->regDmn[1]);
145 PR_EEP("TX Mask", pBase->txMask);
146 PR_EEP("RX Mask", pBase->rxMask);
147 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
148 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
149 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
150 AR5416_OPFLAGS_N_2G_HT20));
151 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
152 AR5416_OPFLAGS_N_2G_HT40));
153 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
154 AR5416_OPFLAGS_N_5G_HT20));
155 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
156 AR5416_OPFLAGS_N_5G_HT40));
157 PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
158 PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
159 PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
160 PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
161 PR_EEP("TX Gain type", pBase->txGainType);
162
163 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
164 pBase->macAddr);
165
166 out:
167 if (len > size)
168 len = size;
169
170 return len;
171 }
172 #else
ath9k_hw_4k_dump_eeprom(struct ath_hw * ah,bool dump_base_hdr,u8 * buf,u32 len,u32 size)173 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
174 u8 *buf, u32 len, u32 size)
175 {
176 return 0;
177 }
178 #endif
179
180
181 #undef SIZE_EEPROM_4K
182
ath9k_hw_4k_check_eeprom(struct ath_hw * ah)183 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
184 {
185 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
186 struct ath_common *common = ath9k_hw_common(ah);
187 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
188 u16 *eepdata, temp, magic, magic2;
189 u32 sum = 0, el;
190 bool need_swap = false;
191 int i, addr;
192
193
194 if (!ath9k_hw_use_flash(ah)) {
195 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
196 &magic)) {
197 ath_err(common, "Reading Magic # failed\n");
198 return false;
199 }
200
201 ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic);
202
203 if (magic != AR5416_EEPROM_MAGIC) {
204 magic2 = swab16(magic);
205
206 if (magic2 == AR5416_EEPROM_MAGIC) {
207 need_swap = true;
208 eepdata = (u16 *) (&ah->eeprom);
209
210 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
211 temp = swab16(*eepdata);
212 *eepdata = temp;
213 eepdata++;
214 }
215 } else {
216 ath_err(common,
217 "Invalid EEPROM Magic. Endianness mismatch.\n");
218 return -EINVAL;
219 }
220 }
221 }
222
223 ath_dbg(common, EEPROM, "need_swap = %s\n",
224 need_swap ? "True" : "False");
225
226 if (need_swap)
227 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
228 else
229 el = ah->eeprom.map4k.baseEepHeader.length;
230
231 if (el > sizeof(struct ar5416_eeprom_4k))
232 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
233 else
234 el = el / sizeof(u16);
235
236 eepdata = (u16 *)(&ah->eeprom);
237
238 for (i = 0; i < el; i++)
239 sum ^= *eepdata++;
240
241 if (need_swap) {
242 u32 integer;
243 u16 word;
244
245 ath_dbg(common, EEPROM,
246 "EEPROM Endianness is not native.. Changing\n");
247
248 word = swab16(eep->baseEepHeader.length);
249 eep->baseEepHeader.length = word;
250
251 word = swab16(eep->baseEepHeader.checksum);
252 eep->baseEepHeader.checksum = word;
253
254 word = swab16(eep->baseEepHeader.version);
255 eep->baseEepHeader.version = word;
256
257 word = swab16(eep->baseEepHeader.regDmn[0]);
258 eep->baseEepHeader.regDmn[0] = word;
259
260 word = swab16(eep->baseEepHeader.regDmn[1]);
261 eep->baseEepHeader.regDmn[1] = word;
262
263 word = swab16(eep->baseEepHeader.rfSilent);
264 eep->baseEepHeader.rfSilent = word;
265
266 word = swab16(eep->baseEepHeader.blueToothOptions);
267 eep->baseEepHeader.blueToothOptions = word;
268
269 word = swab16(eep->baseEepHeader.deviceCap);
270 eep->baseEepHeader.deviceCap = word;
271
272 integer = swab32(eep->modalHeader.antCtrlCommon);
273 eep->modalHeader.antCtrlCommon = integer;
274
275 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
276 integer = swab32(eep->modalHeader.antCtrlChain[i]);
277 eep->modalHeader.antCtrlChain[i] = integer;
278 }
279
280 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
281 word = swab16(eep->modalHeader.spurChans[i].spurChan);
282 eep->modalHeader.spurChans[i].spurChan = word;
283 }
284 }
285
286 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
287 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
288 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
289 sum, ah->eep_ops->get_eeprom_ver(ah));
290 return -EINVAL;
291 }
292
293 return 0;
294 #undef EEPROM_4K_SIZE
295 }
296
ath9k_hw_4k_get_eeprom(struct ath_hw * ah,enum eeprom_param param)297 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
298 enum eeprom_param param)
299 {
300 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
301 struct modal_eep_4k_header *pModal = &eep->modalHeader;
302 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
303 u16 ver_minor;
304
305 ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
306
307 switch (param) {
308 case EEP_NFTHRESH_2:
309 return pModal->noiseFloorThreshCh[0];
310 case EEP_MAC_LSW:
311 return get_unaligned_be16(pBase->macAddr);
312 case EEP_MAC_MID:
313 return get_unaligned_be16(pBase->macAddr + 2);
314 case EEP_MAC_MSW:
315 return get_unaligned_be16(pBase->macAddr + 4);
316 case EEP_REG_0:
317 return pBase->regDmn[0];
318 case EEP_OP_CAP:
319 return pBase->deviceCap;
320 case EEP_OP_MODE:
321 return pBase->opCapFlags;
322 case EEP_RF_SILENT:
323 return pBase->rfSilent;
324 case EEP_OB_2:
325 return pModal->ob_0;
326 case EEP_DB_2:
327 return pModal->db1_1;
328 case EEP_MINOR_REV:
329 return ver_minor;
330 case EEP_TX_MASK:
331 return pBase->txMask;
332 case EEP_RX_MASK:
333 return pBase->rxMask;
334 case EEP_FRAC_N_5G:
335 return 0;
336 case EEP_PWR_TABLE_OFFSET:
337 return AR5416_PWR_TABLE_OFFSET_DB;
338 case EEP_MODAL_VER:
339 return pModal->version;
340 case EEP_ANT_DIV_CTL1:
341 return pModal->antdiv_ctl1;
342 case EEP_TXGAIN_TYPE:
343 return pBase->txGainType;
344 case EEP_ANTENNA_GAIN_2G:
345 return pModal->antennaGainCh[0];
346 default:
347 return 0;
348 }
349 }
350
ath9k_hw_set_4k_power_cal_table(struct ath_hw * ah,struct ath9k_channel * chan)351 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
352 struct ath9k_channel *chan)
353 {
354 struct ath_common *common = ath9k_hw_common(ah);
355 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
356 struct cal_data_per_freq_4k *pRawDataset;
357 u8 *pCalBChans = NULL;
358 u16 pdGainOverlap_t2;
359 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
360 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
361 u16 numPiers, i, j;
362 u16 numXpdGain, xpdMask;
363 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
364 u32 reg32, regOffset, regChainOffset;
365
366 xpdMask = pEepData->modalHeader.xpdGain;
367
368 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
369 AR5416_EEP_MINOR_VER_2) {
370 pdGainOverlap_t2 =
371 pEepData->modalHeader.pdGainOverlap;
372 } else {
373 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
374 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
375 }
376
377 pCalBChans = pEepData->calFreqPier2G;
378 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
379
380 numXpdGain = 0;
381
382 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
383 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
384 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
385 break;
386 xpdGainValues[numXpdGain] =
387 (u16)(AR5416_PD_GAINS_IN_MASK - i);
388 numXpdGain++;
389 }
390 }
391
392 ENABLE_REG_RMW_BUFFER(ah);
393 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
394 (numXpdGain - 1) & 0x3);
395 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
396 xpdGainValues[0]);
397 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
398 xpdGainValues[1]);
399 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
400 REG_RMW_BUFFER_FLUSH(ah);
401
402 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
403 regChainOffset = i * 0x1000;
404
405 if (pEepData->baseEepHeader.txMask & (1 << i)) {
406 pRawDataset = pEepData->calPierData2G[i];
407
408 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
409 pRawDataset, pCalBChans,
410 numPiers, pdGainOverlap_t2,
411 gainBoundaries,
412 pdadcValues, numXpdGain);
413
414 ENABLE_REGWRITE_BUFFER(ah);
415
416 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
417 SM(pdGainOverlap_t2,
418 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
419 | SM(gainBoundaries[0],
420 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
421 | SM(gainBoundaries[1],
422 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
423 | SM(gainBoundaries[2],
424 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
425 | SM(gainBoundaries[3],
426 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
427
428 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
429 for (j = 0; j < 32; j++) {
430 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
431 REG_WRITE(ah, regOffset, reg32);
432
433 ath_dbg(common, EEPROM,
434 "PDADC (%d,%4x): %4.4x %8.8x\n",
435 i, regChainOffset, regOffset,
436 reg32);
437 ath_dbg(common, EEPROM,
438 "PDADC: Chain %d | "
439 "PDADC %3d Value %3d | "
440 "PDADC %3d Value %3d | "
441 "PDADC %3d Value %3d | "
442 "PDADC %3d Value %3d |\n",
443 i, 4 * j, pdadcValues[4 * j],
444 4 * j + 1, pdadcValues[4 * j + 1],
445 4 * j + 2, pdadcValues[4 * j + 2],
446 4 * j + 3, pdadcValues[4 * j + 3]);
447
448 regOffset += 4;
449 }
450
451 REGWRITE_BUFFER_FLUSH(ah);
452 }
453 }
454 }
455
ath9k_hw_set_4k_power_per_rate_table(struct ath_hw * ah,struct ath9k_channel * chan,int16_t * ratesArray,u16 cfgCtl,u16 antenna_reduction,u16 powerLimit)456 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
457 struct ath9k_channel *chan,
458 int16_t *ratesArray,
459 u16 cfgCtl,
460 u16 antenna_reduction,
461 u16 powerLimit)
462 {
463 #define CMP_TEST_GRP \
464 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
465 pEepData->ctlIndex[i]) \
466 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
467 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
468
469 int i;
470 u16 twiceMinEdgePower;
471 u16 twiceMaxEdgePower;
472 u16 scaledPower = 0, minCtlPower;
473 u16 numCtlModes;
474 const u16 *pCtlMode;
475 u16 ctlMode, freq;
476 struct chan_centers centers;
477 struct cal_ctl_data_4k *rep;
478 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
479 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
480 0, { 0, 0, 0, 0}
481 };
482 struct cal_target_power_leg targetPowerOfdmExt = {
483 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
484 0, { 0, 0, 0, 0 }
485 };
486 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
487 0, {0, 0, 0, 0}
488 };
489 static const u16 ctlModesFor11g[] = {
490 CTL_11B, CTL_11G, CTL_2GHT20,
491 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
492 };
493
494 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
495
496 scaledPower = powerLimit - antenna_reduction;
497 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
498 pCtlMode = ctlModesFor11g;
499
500 ath9k_hw_get_legacy_target_powers(ah, chan,
501 pEepData->calTargetPowerCck,
502 AR5416_NUM_2G_CCK_TARGET_POWERS,
503 &targetPowerCck, 4, false);
504 ath9k_hw_get_legacy_target_powers(ah, chan,
505 pEepData->calTargetPower2G,
506 AR5416_NUM_2G_20_TARGET_POWERS,
507 &targetPowerOfdm, 4, false);
508 ath9k_hw_get_target_powers(ah, chan,
509 pEepData->calTargetPower2GHT20,
510 AR5416_NUM_2G_20_TARGET_POWERS,
511 &targetPowerHt20, 8, false);
512
513 if (IS_CHAN_HT40(chan)) {
514 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
515 ath9k_hw_get_target_powers(ah, chan,
516 pEepData->calTargetPower2GHT40,
517 AR5416_NUM_2G_40_TARGET_POWERS,
518 &targetPowerHt40, 8, true);
519 ath9k_hw_get_legacy_target_powers(ah, chan,
520 pEepData->calTargetPowerCck,
521 AR5416_NUM_2G_CCK_TARGET_POWERS,
522 &targetPowerCckExt, 4, true);
523 ath9k_hw_get_legacy_target_powers(ah, chan,
524 pEepData->calTargetPower2G,
525 AR5416_NUM_2G_20_TARGET_POWERS,
526 &targetPowerOfdmExt, 4, true);
527 }
528
529 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
530 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
531 (pCtlMode[ctlMode] == CTL_2GHT40);
532
533 if (isHt40CtlMode)
534 freq = centers.synth_center;
535 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
536 freq = centers.ext_center;
537 else
538 freq = centers.ctl_center;
539
540 twiceMaxEdgePower = MAX_RATE_POWER;
541
542 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
543 pEepData->ctlIndex[i]; i++) {
544
545 if (CMP_TEST_GRP) {
546 rep = &(pEepData->ctlData[i]);
547
548 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
549 freq,
550 rep->ctlEdges[
551 ar5416_get_ntxchains(ah->txchainmask) - 1],
552 IS_CHAN_2GHZ(chan),
553 AR5416_EEP4K_NUM_BAND_EDGES);
554
555 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
556 twiceMaxEdgePower =
557 min(twiceMaxEdgePower,
558 twiceMinEdgePower);
559 } else {
560 twiceMaxEdgePower = twiceMinEdgePower;
561 break;
562 }
563 }
564 }
565
566 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
567
568 switch (pCtlMode[ctlMode]) {
569 case CTL_11B:
570 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
571 targetPowerCck.tPow2x[i] =
572 min((u16)targetPowerCck.tPow2x[i],
573 minCtlPower);
574 }
575 break;
576 case CTL_11G:
577 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
578 targetPowerOfdm.tPow2x[i] =
579 min((u16)targetPowerOfdm.tPow2x[i],
580 minCtlPower);
581 }
582 break;
583 case CTL_2GHT20:
584 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
585 targetPowerHt20.tPow2x[i] =
586 min((u16)targetPowerHt20.tPow2x[i],
587 minCtlPower);
588 }
589 break;
590 case CTL_11B_EXT:
591 targetPowerCckExt.tPow2x[0] =
592 min((u16)targetPowerCckExt.tPow2x[0],
593 minCtlPower);
594 break;
595 case CTL_11G_EXT:
596 targetPowerOfdmExt.tPow2x[0] =
597 min((u16)targetPowerOfdmExt.tPow2x[0],
598 minCtlPower);
599 break;
600 case CTL_2GHT40:
601 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
602 targetPowerHt40.tPow2x[i] =
603 min((u16)targetPowerHt40.tPow2x[i],
604 minCtlPower);
605 }
606 break;
607 default:
608 break;
609 }
610 }
611
612 ratesArray[rate6mb] =
613 ratesArray[rate9mb] =
614 ratesArray[rate12mb] =
615 ratesArray[rate18mb] =
616 ratesArray[rate24mb] =
617 targetPowerOfdm.tPow2x[0];
618
619 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
620 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
621 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
622 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
623
624 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
625 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
626
627 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
628 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
629 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
630 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
631
632 if (IS_CHAN_HT40(chan)) {
633 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
634 ratesArray[rateHt40_0 + i] =
635 targetPowerHt40.tPow2x[i];
636 }
637 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
638 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
639 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
640 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
641 }
642
643 #undef CMP_TEST_GRP
644 }
645
ath9k_hw_4k_set_txpower(struct ath_hw * ah,struct ath9k_channel * chan,u16 cfgCtl,u8 twiceAntennaReduction,u8 powerLimit,bool test)646 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
647 struct ath9k_channel *chan,
648 u16 cfgCtl,
649 u8 twiceAntennaReduction,
650 u8 powerLimit, bool test)
651 {
652 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
653 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
654 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
655 int16_t ratesArray[Ar5416RateSize];
656 u8 ht40PowerIncForPdadc = 2;
657 int i;
658
659 memset(ratesArray, 0, sizeof(ratesArray));
660
661 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
662 AR5416_EEP_MINOR_VER_2) {
663 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
664 }
665
666 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
667 &ratesArray[0], cfgCtl,
668 twiceAntennaReduction,
669 powerLimit);
670
671 ath9k_hw_set_4k_power_cal_table(ah, chan);
672
673 regulatory->max_power_level = 0;
674 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
675 if (ratesArray[i] > MAX_RATE_POWER)
676 ratesArray[i] = MAX_RATE_POWER;
677
678 if (ratesArray[i] > regulatory->max_power_level)
679 regulatory->max_power_level = ratesArray[i];
680 }
681
682 if (test)
683 return;
684
685 for (i = 0; i < Ar5416RateSize; i++)
686 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
687
688 ENABLE_REGWRITE_BUFFER(ah);
689
690 /* OFDM power per rate */
691 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
692 ATH9K_POW_SM(ratesArray[rate18mb], 24)
693 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
694 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
695 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
696 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
697 ATH9K_POW_SM(ratesArray[rate54mb], 24)
698 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
699 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
700 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
701
702 /* CCK power per rate */
703 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
704 ATH9K_POW_SM(ratesArray[rate2s], 24)
705 | ATH9K_POW_SM(ratesArray[rate2l], 16)
706 | ATH9K_POW_SM(ratesArray[rateXr], 8)
707 | ATH9K_POW_SM(ratesArray[rate1l], 0));
708 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
709 ATH9K_POW_SM(ratesArray[rate11s], 24)
710 | ATH9K_POW_SM(ratesArray[rate11l], 16)
711 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
712 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
713
714 /* HT20 power per rate */
715 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
716 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
717 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
718 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
719 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
720 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
721 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
722 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
723 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
724 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
725
726 /* HT40 power per rate */
727 if (IS_CHAN_HT40(chan)) {
728 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
729 ATH9K_POW_SM(ratesArray[rateHt40_3] +
730 ht40PowerIncForPdadc, 24)
731 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
732 ht40PowerIncForPdadc, 16)
733 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
734 ht40PowerIncForPdadc, 8)
735 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
736 ht40PowerIncForPdadc, 0));
737 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
738 ATH9K_POW_SM(ratesArray[rateHt40_7] +
739 ht40PowerIncForPdadc, 24)
740 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
741 ht40PowerIncForPdadc, 16)
742 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
743 ht40PowerIncForPdadc, 8)
744 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
745 ht40PowerIncForPdadc, 0));
746 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
747 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
748 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
749 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
750 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
751 }
752
753 /* TPC initializations */
754 if (ah->tpc_enabled) {
755 int ht40_delta;
756
757 ht40_delta = (IS_CHAN_HT40(chan)) ? ht40PowerIncForPdadc : 0;
758 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta);
759 /* Enable TPC */
760 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX,
761 MAX_RATE_POWER | AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
762 } else {
763 /* Disable TPC */
764 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER);
765 }
766
767 REGWRITE_BUFFER_FLUSH(ah);
768 }
769
ath9k_hw_4k_set_gain(struct ath_hw * ah,struct modal_eep_4k_header * pModal,struct ar5416_eeprom_4k * eep,u8 txRxAttenLocal)770 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
771 struct modal_eep_4k_header *pModal,
772 struct ar5416_eeprom_4k *eep,
773 u8 txRxAttenLocal)
774 {
775 ENABLE_REG_RMW_BUFFER(ah);
776 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0,
777 pModal->antCtrlChain[0], 0);
778
779 REG_RMW(ah, AR_PHY_TIMING_CTRL4(0),
780 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
781 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF),
782 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF);
783
784 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
785 AR5416_EEP_MINOR_VER_3) {
786 txRxAttenLocal = pModal->txRxAttenCh[0];
787
788 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
789 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
790 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
791 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
792 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
793 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
794 pModal->xatten2Margin[0]);
795 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
796 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
797
798 /* Set the block 1 value to block 0 value */
799 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
800 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
801 pModal->bswMargin[0]);
802 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
803 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
804 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
805 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
806 pModal->xatten2Margin[0]);
807 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
808 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
809 pModal->xatten2Db[0]);
810 }
811
812 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
813 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
814 REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
815 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
816
817 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
818 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
819 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
820 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
821 REG_RMW_BUFFER_FLUSH(ah);
822 }
823
824 /*
825 * Read EEPROM header info and program the device for correct operation
826 * given the channel value.
827 */
ath9k_hw_4k_set_board_values(struct ath_hw * ah,struct ath9k_channel * chan)828 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
829 struct ath9k_channel *chan)
830 {
831 struct ath9k_hw_capabilities *pCap = &ah->caps;
832 struct modal_eep_4k_header *pModal;
833 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
834 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
835 u8 txRxAttenLocal;
836 u8 ob[5], db1[5], db2[5];
837 u8 ant_div_control1, ant_div_control2;
838 u8 bb_desired_scale;
839 u32 regVal;
840
841 pModal = &eep->modalHeader;
842 txRxAttenLocal = 23;
843
844 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
845
846 /* Single chain for 4K EEPROM*/
847 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
848
849 /* Initialize Ant Diversity settings from EEPROM */
850 if (pModal->version >= 3) {
851 ant_div_control1 = pModal->antdiv_ctl1;
852 ant_div_control2 = pModal->antdiv_ctl2;
853
854 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
855 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
856
857 regVal |= SM(ant_div_control1,
858 AR_PHY_9285_ANT_DIV_CTL);
859 regVal |= SM(ant_div_control2,
860 AR_PHY_9285_ANT_DIV_ALT_LNACONF);
861 regVal |= SM((ant_div_control2 >> 2),
862 AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
863 regVal |= SM((ant_div_control1 >> 1),
864 AR_PHY_9285_ANT_DIV_ALT_GAINTB);
865 regVal |= SM((ant_div_control1 >> 2),
866 AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
867
868
869 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
870 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
871 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
872 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
873 regVal |= SM((ant_div_control1 >> 3),
874 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
875
876 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
877 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
878
879 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
880 /*
881 * If diversity combining is enabled,
882 * set MAIN to LNA1 and ALT to LNA2 initially.
883 */
884 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
885 regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
886 AR_PHY_9285_ANT_DIV_ALT_LNACONF));
887
888 regVal |= (ATH_ANT_DIV_COMB_LNA1 <<
889 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S);
890 regVal |= (ATH_ANT_DIV_COMB_LNA2 <<
891 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S);
892 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));
893 regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);
894 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
895 }
896 }
897
898 if (pModal->version >= 2) {
899 ob[0] = pModal->ob_0;
900 ob[1] = pModal->ob_1;
901 ob[2] = pModal->ob_2;
902 ob[3] = pModal->ob_3;
903 ob[4] = pModal->ob_4;
904
905 db1[0] = pModal->db1_0;
906 db1[1] = pModal->db1_1;
907 db1[2] = pModal->db1_2;
908 db1[3] = pModal->db1_3;
909 db1[4] = pModal->db1_4;
910
911 db2[0] = pModal->db2_0;
912 db2[1] = pModal->db2_1;
913 db2[2] = pModal->db2_2;
914 db2[3] = pModal->db2_3;
915 db2[4] = pModal->db2_4;
916 } else if (pModal->version == 1) {
917 ob[0] = pModal->ob_0;
918 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
919 db1[0] = pModal->db1_0;
920 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
921 db2[0] = pModal->db2_0;
922 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
923 } else {
924 int i;
925
926 for (i = 0; i < 5; i++) {
927 ob[i] = pModal->ob_0;
928 db1[i] = pModal->db1_0;
929 db2[i] = pModal->db1_0;
930 }
931 }
932
933 ENABLE_REG_RMW_BUFFER(ah);
934 if (AR_SREV_9271(ah)) {
935 ath9k_hw_analog_shift_rmw(ah,
936 AR9285_AN_RF2G3,
937 AR9271_AN_RF2G3_OB_cck,
938 AR9271_AN_RF2G3_OB_cck_S,
939 ob[0]);
940 ath9k_hw_analog_shift_rmw(ah,
941 AR9285_AN_RF2G3,
942 AR9271_AN_RF2G3_OB_psk,
943 AR9271_AN_RF2G3_OB_psk_S,
944 ob[1]);
945 ath9k_hw_analog_shift_rmw(ah,
946 AR9285_AN_RF2G3,
947 AR9271_AN_RF2G3_OB_qam,
948 AR9271_AN_RF2G3_OB_qam_S,
949 ob[2]);
950 ath9k_hw_analog_shift_rmw(ah,
951 AR9285_AN_RF2G3,
952 AR9271_AN_RF2G3_DB_1,
953 AR9271_AN_RF2G3_DB_1_S,
954 db1[0]);
955 ath9k_hw_analog_shift_rmw(ah,
956 AR9285_AN_RF2G4,
957 AR9271_AN_RF2G4_DB_2,
958 AR9271_AN_RF2G4_DB_2_S,
959 db2[0]);
960 } else {
961 ath9k_hw_analog_shift_rmw(ah,
962 AR9285_AN_RF2G3,
963 AR9285_AN_RF2G3_OB_0,
964 AR9285_AN_RF2G3_OB_0_S,
965 ob[0]);
966 ath9k_hw_analog_shift_rmw(ah,
967 AR9285_AN_RF2G3,
968 AR9285_AN_RF2G3_OB_1,
969 AR9285_AN_RF2G3_OB_1_S,
970 ob[1]);
971 ath9k_hw_analog_shift_rmw(ah,
972 AR9285_AN_RF2G3,
973 AR9285_AN_RF2G3_OB_2,
974 AR9285_AN_RF2G3_OB_2_S,
975 ob[2]);
976 ath9k_hw_analog_shift_rmw(ah,
977 AR9285_AN_RF2G3,
978 AR9285_AN_RF2G3_OB_3,
979 AR9285_AN_RF2G3_OB_3_S,
980 ob[3]);
981 ath9k_hw_analog_shift_rmw(ah,
982 AR9285_AN_RF2G3,
983 AR9285_AN_RF2G3_OB_4,
984 AR9285_AN_RF2G3_OB_4_S,
985 ob[4]);
986
987 ath9k_hw_analog_shift_rmw(ah,
988 AR9285_AN_RF2G3,
989 AR9285_AN_RF2G3_DB1_0,
990 AR9285_AN_RF2G3_DB1_0_S,
991 db1[0]);
992 ath9k_hw_analog_shift_rmw(ah,
993 AR9285_AN_RF2G3,
994 AR9285_AN_RF2G3_DB1_1,
995 AR9285_AN_RF2G3_DB1_1_S,
996 db1[1]);
997 ath9k_hw_analog_shift_rmw(ah,
998 AR9285_AN_RF2G3,
999 AR9285_AN_RF2G3_DB1_2,
1000 AR9285_AN_RF2G3_DB1_2_S,
1001 db1[2]);
1002 ath9k_hw_analog_shift_rmw(ah,
1003 AR9285_AN_RF2G4,
1004 AR9285_AN_RF2G4_DB1_3,
1005 AR9285_AN_RF2G4_DB1_3_S,
1006 db1[3]);
1007 ath9k_hw_analog_shift_rmw(ah,
1008 AR9285_AN_RF2G4,
1009 AR9285_AN_RF2G4_DB1_4,
1010 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1011
1012 ath9k_hw_analog_shift_rmw(ah,
1013 AR9285_AN_RF2G4,
1014 AR9285_AN_RF2G4_DB2_0,
1015 AR9285_AN_RF2G4_DB2_0_S,
1016 db2[0]);
1017 ath9k_hw_analog_shift_rmw(ah,
1018 AR9285_AN_RF2G4,
1019 AR9285_AN_RF2G4_DB2_1,
1020 AR9285_AN_RF2G4_DB2_1_S,
1021 db2[1]);
1022 ath9k_hw_analog_shift_rmw(ah,
1023 AR9285_AN_RF2G4,
1024 AR9285_AN_RF2G4_DB2_2,
1025 AR9285_AN_RF2G4_DB2_2_S,
1026 db2[2]);
1027 ath9k_hw_analog_shift_rmw(ah,
1028 AR9285_AN_RF2G4,
1029 AR9285_AN_RF2G4_DB2_3,
1030 AR9285_AN_RF2G4_DB2_3_S,
1031 db2[3]);
1032 ath9k_hw_analog_shift_rmw(ah,
1033 AR9285_AN_RF2G4,
1034 AR9285_AN_RF2G4_DB2_4,
1035 AR9285_AN_RF2G4_DB2_4_S,
1036 db2[4]);
1037 }
1038 REG_RMW_BUFFER_FLUSH(ah);
1039
1040 ENABLE_REG_RMW_BUFFER(ah);
1041 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1042 pModal->switchSettling);
1043 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1044 pModal->adcDesiredSize);
1045
1046 REG_RMW(ah, AR_PHY_RF_CTL4,
1047 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1048 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1049 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1050 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON), 0);
1051
1052 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1053 pModal->txEndToRxOn);
1054
1055 if (AR_SREV_9271_10(ah))
1056 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1057 pModal->txEndToRxOn);
1058 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1059 pModal->thresh62);
1060 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1061 pModal->thresh62);
1062
1063 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1064 AR5416_EEP_MINOR_VER_2) {
1065 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1066 pModal->txFrameToDataStart);
1067 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1068 pModal->txFrameToPaOn);
1069 }
1070
1071 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1072 AR5416_EEP_MINOR_VER_3) {
1073 if (IS_CHAN_HT40(chan))
1074 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1075 AR_PHY_SETTLING_SWITCH,
1076 pModal->swSettleHt40);
1077 }
1078
1079 REG_RMW_BUFFER_FLUSH(ah);
1080
1081 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1082 EEP_4K_BB_DESIRED_SCALE_MASK);
1083 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1084 u32 pwrctrl, mask, clr;
1085
1086 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1087 pwrctrl = mask * bb_desired_scale;
1088 clr = mask * 0x1f;
1089 ENABLE_REG_RMW_BUFFER(ah);
1090 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1091 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1092 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1093
1094 mask = BIT(0)|BIT(5)|BIT(15);
1095 pwrctrl = mask * bb_desired_scale;
1096 clr = mask * 0x1f;
1097 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1098
1099 mask = BIT(0)|BIT(5);
1100 pwrctrl = mask * bb_desired_scale;
1101 clr = mask * 0x1f;
1102 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1103 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1104 REG_RMW_BUFFER_FLUSH(ah);
1105 }
1106 }
1107
ath9k_hw_4k_get_spur_channel(struct ath_hw * ah,u16 i,bool is2GHz)1108 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1109 {
1110 return ah->eeprom.map4k.modalHeader.spurChans[i].spurChan;
1111 }
1112
1113 const struct eeprom_ops eep_4k_ops = {
1114 .check_eeprom = ath9k_hw_4k_check_eeprom,
1115 .get_eeprom = ath9k_hw_4k_get_eeprom,
1116 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1117 .dump_eeprom = ath9k_hw_4k_dump_eeprom,
1118 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1119 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1120 .set_board_values = ath9k_hw_4k_set_board_values,
1121 .set_txpower = ath9k_hw_4k_set_txpower,
1122 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1123 };
1124