183 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
189 	dma_ch[channel].regs->start_addr = addr;  in set_dma_start_addr()
193 	dma_ch[channel].regs->next_desc_ptr = addr;  in set_dma_next_desc_addr()
197 	dma_ch[channel].regs->curr_desc_ptr = addr;  in set_dma_curr_desc_addr()
201 	dma_ch[channel].regs->x_count = x_count;  in set_dma_x_count()
205 	dma_ch[channel].regs->y_count = y_count;  in set_dma_y_count()
209 	dma_ch[channel].regs->x_modify = x_modify;  in set_dma_x_modify()
213 	dma_ch[channel].regs->y_modify = y_modify;  in set_dma_y_modify()
217 	dma_ch[channel].regs->cfg = config;  in set_dma_config()
221 	dma_ch[channel].regs->curr_addr_ptr = addr;  in set_dma_curr_addr()
266 	return dma_ch[channel].regs->irq_status;  in get_dma_curr_irqstat()
270 	return dma_ch[channel].regs->curr_x_count;  in get_dma_curr_xcount()
274 	return dma_ch[channel].regs->curr_y_count;  in get_dma_curr_ycount()
278 	return dma_ch[channel].regs->next_desc_ptr;  in get_dma_next_desc_ptr()
282 	return dma_ch[channel].regs->curr_desc_ptr;  in get_dma_curr_desc_ptr()
286 	return dma_ch[channel].regs->cfg;  in get_dma_config()
290 	return dma_ch[channel].regs->curr_addr_ptr;  in get_dma_curr_addr()
301 	dma_ch[channel].regs->next_desc_ptr = sg;  in set_dma_sg()
302 	dma_ch[channel].regs->cfg =  in set_dma_sg()
303 		(dma_ch[channel].regs->cfg & ~NDSIZE) |  in set_dma_sg()
309 	return atomic_read(&dma_ch[channel].chan_status);  in dma_channel_active()
314 	dma_ch[channel].regs->cfg &= ~DMAEN;  in disable_dma()
319 	dma_ch[channel].regs->curr_x_count = 0;  in enable_dma()
320 	dma_ch[channel].regs->curr_y_count = 0;  in enable_dma()
321 	dma_ch[channel].regs->cfg |= DMAEN;  in enable_dma()
327 	disable_irq(dma_ch[channel].irq);  in dma_disable_irq()
331 	disable_irq_nosync(dma_ch[channel].irq);  in dma_disable_irq_nosync()
335 	enable_irq(dma_ch[channel].irq);  in dma_enable_irq()
339 	dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;  in clear_dma_irqstat()