Lines Matching refs:d
22 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
23 move.d $r0, [R_WAITSTATES]
25 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
26 move.d $r0, [R_BUS_CONFIG]
29 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
30 move.d $r0, [R_DRAM_CONFIG]
32 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
33 move.d $r0, [R_DRAM_TIMING]
42 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
43 move.d $r0, [R_SDRAM_CONFIG]
52 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
53 and.d 0x00ff0000, $r2
57 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
58 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
59 move.d $r1, $r3
60 and.d 0x03, $r1 ; Get CAS latency
61 and.d 0x1000, $r3 ; 50 or 100 MHz?
65 cmp.d 0x00, $r1 ; CAS latency = 2?
68 or.d 0x20, $r2 ; CAS latency = 3
72 cmp.d 0x01, $r1 ; CAS latency = 2?
75 or.d 0x20, $r2 ; CAS latency = 3
77 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
78 and.d 0x800000, $r1 ; DRAM width is bit 23
85 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
86 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
87 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
88 move.d $r1, $r5
89 or.d 0x0000c000, $r1 ; ref = disable
91 or.d $r2, $r1
92 move.d $r1, [R_SDRAM_TIMING]
95 move.d 10000, $r2
100 move.d _sdram_commands_start, $r2
101 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
102 move.d _sdram_commands_end, $r3
103 and.d 0x000fffff, $r3
104 1: clear.d $r4
107 or.d $r1, $r4
108 move.d $r4, [R_SDRAM_TIMING]
114 cmp.d $r2, $r3
117 move.d $r5, [R_SDRAM_TIMING]