69 		T  = 0,  enumerator
74 	#define T  macro
812 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
813 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
814 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
821 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
822 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
823 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
855 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
856 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
857 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
882 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
883 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
886 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
887 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
892 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
893 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
896 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
897 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
900 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
919 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
920 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
923 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
924 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
929 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
930 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
933 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
934 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
940 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
941 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
944 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
945 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
963 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
964 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
967 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
968 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
973 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
974 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
977 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
978 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
981 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
1005 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1006 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1009 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1010 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1016 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1017 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1020 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1021 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1134 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1135 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1138 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1139 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1144 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1145 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1148 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1149 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1152 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1172 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1175 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1582 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1633 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1648 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()