Lines Matching refs:t0
59 li t0, LSU_DEFEATURE
60 mfcr t1, t0
64 mtcr t1, t0
66 li t0, ICU_DEFEATURE
67 mfcr t1, t0
69 mtcr t1, t0
71 li t0, SCHED_DEFEATURE
73 mtcr t1, t0
82 mfc0 t0, CP0_PAGEMASK, 1
84 or t0, t1
85 mtc0 t0, CP0_PAGEMASK, 1
94 mfc0 t0, CP0_PRID
95 andi t0, t0, PRID_IMP_MASK
96 slt t1, t0, 0x1200
101 li t0, LSU_DEBUG_DATA0
107 mtcr zero, t0
115 mtcr zero, t0
131 li t0, 0x80000000
133 16: cache Index_Writeback_Inv_D, 0(t0)
134 addiu t0, t0, 32
135 bne t0, t1, 16b
173 mfc0 t0, CP0_PRID /* processor ID */
174 andi t0, PRID_IMP_MASK
176 beq t0, t1, 2f /* does not need to set coherent */
180 beq t0, t1, 2f /* does not need to set coherent */
184 mfc0 t0, CP0_EBASE
190 srl t0, t0, 2
191 and t0, t0, 0x7 /* t0 <- core */
193 sll t0, t1, t0
194 nor t0, t0, zero /* t0 <- ~(1 << core) */
198 and t1, t1, t0
220 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
221 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
222 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
223 mfcr t2, t0
225 mtcr t2, t0
246 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
247 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
252 li t0, IFU_BRUB_RESERVE
254 mtcr t1, t0