76 pciauto_setup_bars(struct pci_dev *dev, int bar_limit)  in pciauto_setup_bars()  argument
88 		pci_write_config_dword(dev, bar, 0xffffffff);  in pciauto_setup_bars()
89 		pci_read_config_dword(dev, bar, &bar_size);  in pciauto_setup_bars()
117 		pci_write_config_dword(dev, bar, *upper_limit);  in pciauto_setup_bars()
126 			pci_write_config_dword(dev, (bar+=4), 0x00000000);  in pciauto_setup_bars()
135 pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn)  in pciauto_setup_irq()  argument
140 	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);  in pciauto_setup_irq()
148 		irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin);  in pciauto_setup_irq()
155 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);  in pciauto_setup_irq()
160 pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus,  in pciauto_prescan_setup_bridge()  argument
164 	pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus);  in pciauto_prescan_setup_bridge()
165 	pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1);  in pciauto_prescan_setup_bridge()
166 	pci_write_config_byte(dev, PCI_SUBORDINATE_BUS,	0xff);  in pciauto_prescan_setup_bridge()
177 	pci_write_config_word(dev, PCI_MEMORY_LIMIT,  in pciauto_prescan_setup_bridge()
179 	pci_write_config_byte(dev, PCI_IO_LIMIT,  in pciauto_prescan_setup_bridge()
181 	pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,  in pciauto_prescan_setup_bridge()
186 pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus,  in pciauto_postscan_setup_bridge()  argument
192 	pci_write_config_byte(dev, PCI_SUBORDINATE_BUS,	sub_bus);  in pciauto_postscan_setup_bridge()
202 	pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16);  in pciauto_postscan_setup_bridge()
205 	pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,  in pciauto_postscan_setup_bridge()
210 	pci_write_config_word(dev, PCI_PREF_MEMORY_BASE,  in pciauto_postscan_setup_bridge()
218 	pci_write_config_byte(dev, PCI_IO_BASE,  in pciauto_postscan_setup_bridge()
220 	pci_write_config_word(dev, PCI_IO_BASE_UPPER16,  in pciauto_postscan_setup_bridge()
224 	pci_read_config_dword(dev, PCI_COMMAND, &cmdstat);  in pciauto_postscan_setup_bridge()
225 	pci_write_config_dword(dev, PCI_COMMAND,  in pciauto_postscan_setup_bridge()
242 	struct pci_dev *dev = &pciauto_dev;  in pciauto_bus_scan()  local
274 		if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type))  in pciauto_bus_scan()
279 		pci_read_config_word(dev, PCI_VENDOR_ID, &vid);  in pciauto_bus_scan()
286 		pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class);  in pciauto_bus_scan()
296 			pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1);  in pciauto_bus_scan()
298 			pciauto_prescan_setup_bridge(dev, current_bus, sub_bus,  in pciauto_bus_scan()
301 			pciauto_postscan_setup_bridge(dev, current_bus, sub_bus,  in pciauto_bus_scan()
316 			pci_read_config_byte(dev, PCI_CLASS_PROG, &prg_iface);  in pciauto_bus_scan()
331 		pci_read_config_dword(dev, PCI_COMMAND,	&cmdstat);  in pciauto_bus_scan()
332 		pci_write_config_dword(dev, PCI_COMMAND,  in pciauto_bus_scan()
337 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);  in pciauto_bus_scan()
343 		pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5);  in pciauto_bus_scan()
344 		pciauto_setup_irq(pci_ctrl, dev, pci_devfn);  in pciauto_bus_scan()