Lines Matching refs:dt
149 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
189 struct arm_ccn_dt dt; member
471 return &ccn->dt.cmp_mask[i].l; in arm_ccn_pmu_get_cmp_mask()
473 return &ccn->dt.cmp_mask[i].h; in arm_ccn_pmu_get_cmp_mask()
561 return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu); in arm_ccn_pmu_cpumask_show()
657 ccn->dt.pmu_counters_mask)) in arm_ccn_pmu_event_alloc()
661 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; in arm_ccn_pmu_event_alloc()
667 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_event_alloc()
678 ccn->dt.pmu_counters[hw->idx].source = source; in arm_ccn_pmu_event_alloc()
690 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_alloc()
695 ccn->dt.pmu_counters[hw->idx].event = event; in arm_ccn_pmu_event_alloc()
706 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
709 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_event_release()
717 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
720 ccn->dt.pmu_counters[hw->idx].source = NULL; in arm_ccn_pmu_event_release()
721 ccn->dt.pmu_counters[hw->idx].event = NULL; in arm_ccn_pmu_event_release()
764 event->cpu = cpumask_first(&ccn->dt.cpu); in arm_ccn_pmu_event_init()
864 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
867 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
868 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
870 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
871 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
873 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
876 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); in arm_ccn_pmu_read_counter()
920 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
928 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
962 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_watchpoint_config()
967 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; in arm_ccn_pmu_xp_watchpoint_config()
968 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; in arm_ccn_pmu_xp_watchpoint_config()
1010 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_event_config()
1031 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_node_event_config()
1078 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1082 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1086 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1098 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1103 return bitmap_weight(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_active_counters()
1123 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), in arm_ccn_pmu_event_add()
1145 hrtimer_cancel(&ccn->dt.hrtimer); in arm_ccn_pmu_event_del()
1157 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1159 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1166 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1168 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1171 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) in arm_ccn_pmu_overflow_handler() argument
1173 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); in arm_ccn_pmu_overflow_handler()
1179 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_overflow_handler()
1184 struct perf_event *event = dt->pmu_counters[idx].event; in arm_ccn_pmu_overflow_handler()
1201 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, in arm_ccn_pmu_timer_handler() local
1206 arm_ccn_pmu_overflow_handler(dt); in arm_ccn_pmu_timer_handler()
1216 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); in arm_ccn_pmu_offline_cpu() local
1217 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); in arm_ccn_pmu_offline_cpu()
1220 if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) in arm_ccn_pmu_offline_cpu()
1225 perf_pmu_migrate_context(&dt->pmu, cpu, target); in arm_ccn_pmu_offline_cpu()
1226 cpumask_set_cpu(target, &dt->cpu); in arm_ccn_pmu_offline_cpu()
1228 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0); in arm_ccn_pmu_offline_cpu()
1241 ccn->dt.base = ccn->base + CCN_REGION_SIZE; in arm_ccn_pmu_init()
1242 spin_lock_init(&ccn->dt.config_lock); in arm_ccn_pmu_init()
1243 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_init()
1244 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); in arm_ccn_pmu_init()
1246 ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1247 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_init()
1257 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; in arm_ccn_pmu_init()
1258 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; in arm_ccn_pmu_init()
1259 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; in arm_ccn_pmu_init()
1260 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; in arm_ccn_pmu_init()
1261 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; in arm_ccn_pmu_init()
1262 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); in arm_ccn_pmu_init()
1263 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; in arm_ccn_pmu_init()
1264 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); in arm_ccn_pmu_init()
1267 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); in arm_ccn_pmu_init()
1268 if (ccn->dt.id == 0) { in arm_ccn_pmu_init()
1271 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id); in arm_ccn_pmu_init()
1278 snprintf(name, len + 1, "ccn_%d", ccn->dt.id); in arm_ccn_pmu_init()
1282 ccn->dt.pmu = (struct pmu) { in arm_ccn_pmu_init()
1299 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, in arm_ccn_pmu_init()
1301 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; in arm_ccn_pmu_init()
1305 cpumask_set_cpu(get_cpu(), &ccn->dt.cpu); in arm_ccn_pmu_init()
1309 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu); in arm_ccn_pmu_init()
1316 err = perf_pmu_register(&ccn->dt.pmu, name, -1); in arm_ccn_pmu_init()
1321 &ccn->dt.node); in arm_ccn_pmu_init()
1329 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_init()
1332 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1341 &ccn->dt.node); in arm_ccn_pmu_cleanup()
1346 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_cleanup()
1347 perf_pmu_unregister(&ccn->dt.pmu); in arm_ccn_pmu_cleanup()
1348 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_cleanup()
1456 res = arm_ccn_pmu_overflow_handler(&ccn->dt); in arm_ccn_irq_handler()