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Lines Matching refs:aclk

41 	struct axxia_clk aclk;  member
44 #define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
53 struct axxia_clk *aclk = to_axxia_clk(hw); in axxia_pllclk_recalc() local
54 struct axxia_pllclk *pll = to_axxia_pllclk(aclk); in axxia_pllclk_recalc()
58 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
79 struct axxia_clk aclk; member
84 #define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
92 struct axxia_clk *aclk = to_axxia_clk(hw); in axxia_divclk_recalc_rate() local
93 struct axxia_divclk *divclk = to_axxia_divclk(aclk); in axxia_divclk_recalc_rate()
96 regmap_read(aclk->regmap, divclk->reg, &ctrl); in axxia_divclk_recalc_rate()
114 struct axxia_clk aclk; member
119 #define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
126 struct axxia_clk *aclk = to_axxia_clk(hw); in axxia_clkmux_get_parent() local
127 struct axxia_clkmux *mux = to_axxia_clkmux(aclk); in axxia_clkmux_get_parent()
130 regmap_read(aclk->regmap, mux->reg, &ctrl); in axxia_clkmux_get_parent()
146 .aclk.hw.init = &(struct clk_init_data){
158 .aclk.hw.init = &(struct clk_init_data){
170 .aclk.hw.init = &(struct clk_init_data){
182 .aclk.hw.init = &(struct clk_init_data){
194 .aclk.hw.init = &(struct clk_init_data){
210 .aclk.hw.init = &(struct clk_init_data){
224 .aclk.hw.init = &(struct clk_init_data){
238 .aclk.hw.init = &(struct clk_init_data){
252 .aclk.hw.init = &(struct clk_init_data){
266 .aclk.hw.init = &(struct clk_init_data){
280 .aclk.hw.init = &(struct clk_init_data){
294 .aclk.hw.init = &(struct clk_init_data){
308 .aclk.hw.init = &(struct clk_init_data){
323 .aclk.hw.init = &(struct clk_init_data){
342 .aclk.hw.init = &(struct clk_init_data){
359 .aclk.hw.init = &(struct clk_init_data){
376 .aclk.hw.init = &(struct clk_init_data){
393 .aclk.hw.init = &(struct clk_init_data){
410 .aclk.hw.init = &(struct clk_init_data){
427 .aclk.hw.init = &(struct clk_init_data){
444 .aclk.hw.init = &(struct clk_init_data){
461 .aclk.hw.init = &(struct clk_init_data){
476 .aclk.hw.init = &(struct clk_init_data){
494 [AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk,
495 [AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk,
496 [AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk,
497 [AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk,
498 [AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk,
499 [AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk,
500 [AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk,
501 [AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
502 [AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
503 [AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
504 [AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
505 [AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
506 [AXXIA_CLK_PER_DIV] = &clk_per_div.aclk,
507 [AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk,
508 [AXXIA_CLK_FAB] = &clk_fab_mux.aclk,
509 [AXXIA_CLK_SYS] = &clk_sys_mux.aclk,
510 [AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk,
511 [AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk,
512 [AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk,
513 [AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk,
514 [AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk,
515 [AXXIA_CLK_PER] = &clk_per_mux.aclk,
516 [AXXIA_CLK_MMC] = &clk_mmc_mux.aclk,