124 				unsigned long parent_rate)  in vt8500_dclk_recalc_rate()  argument
137 	return parent_rate / div;  in vt8500_dclk_recalc_rate()
167 				unsigned long parent_rate)  in vt8500_dclk_set_rate()  argument
176 	divisor =  parent_rate / rate;  in vt8500_dclk_set_rate()
359 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in vt8500_find_pll_bits()  argument
365 	if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {  in vt8500_find_pll_bits()
371 	if (rate <= parent_rate * 31)  in vt8500_find_pll_bits()
377 	*multiplier = rate / (parent_rate / *prediv);  in vt8500_find_pll_bits()
378 	tclk = (parent_rate / *prediv) * *multiplier;  in vt8500_find_pll_bits()
399 	unsigned long parent_rate, u32 *multiplier, u32 *divisor1,  in wm8650_find_pll_bits()  argument
404 	if (!parent_rate || (rate < 37500000) || (rate > 600000000))  in wm8650_find_pll_bits()
416 		rate_err = O1 % parent_rate;  in wm8650_find_pll_bits()
418 			*multiplier = O1 / parent_rate;  in wm8650_find_pll_bits()
434 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)  in wm8750_get_filter()  argument
437 	u32 freq = (parent_rate / 1000000) / (divisor1 + 1);  in wm8750_get_filter()
461 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in wm8750_find_pll_bits()  argument
474 				tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));  in wm8750_find_pll_bits()
480 					*filter = wm8750_get_filter(parent_rate, div1);  in wm8750_find_pll_bits()
504 	*filter = wm8750_get_filter(parent_rate, *divisor1);  in wm8750_find_pll_bits()
509 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,  in wm8850_find_pll_bits()  argument
522 				tclk = parent_rate * ((mul + 1) * 2) /  in wm8850_find_pll_bits()
556 				unsigned long parent_rate)  in vtwm_pll_set_rate()  argument
568 		ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);  in vtwm_pll_set_rate()
573 		ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);  in vtwm_pll_set_rate()
578 		ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);  in vtwm_pll_set_rate()
583 		ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);  in vtwm_pll_set_rate()
646 				unsigned long parent_rate)  in vtwm_pll_recalc_rate()  argument
654 		pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
658 		pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
662 		pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()
666 		pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);  in vtwm_pll_recalc_rate()